[HELP] Warning: (vsim-3473) Component 'not0' is not bound.

[Luca]

Hello! I have a problem to solve with Modelsim XE II and I'd be very
happy if you helped me. When I compile a vhdl file for a latch-D, I
get a success message; but whet I launch it for a simulation, I always
get the following message:
"Warning: (vsim-3473) Component 'not0' is not bound."

This is the file latch_D.vhd:

entity latch_D is
port(D,Ck:in bit;
Q,Qbarut bit);
end latch_D;
architecture latch_D_arc of latch_D is
component latch_SR
port(S,R,Ck: in bit;
Q,Qbar: out bit);
end component;
component NOT_IMP
port(A: in bit;
Abarut bit);
end component;
signal Dbar : bit;
begin
not0: NOT_IMP
port map (D,Dbar);
latch_SR0: latch_SR
port map (D,Dbar,Ck,Q,Qbar);
end latch_D_arc;

Both not_imp.vhd and latch_SR.vhd give success in compiling and work
great in simulation, but the latch_D doesn't work. Can you help me?
Thanks!!

 

[Egbert Molenkamp]

The design entity in your file not_imp.vhd is simulated correctly but I have
the feeling that the port declaration in entity declaration of not_imp is
not EXACTLY the same is the port declaration in the component declaration.
Copy and paste the port declaration.

Egbert Molenkamp

 

[Just an Illusion]

Hi,

Are you sure that you have compile 'not_imp' architecture in the same
working library that 'latch_d' ?

Compilation doesn't definitively check presence of compiled architecture.
During compilation, tools check only that all component interface (or
prototype) is well defined (via package usage from library or in
architecture_declarative_part).

During the phase of instantiation, the tools try to bound them, and that
is the possible source of the warning (if the component isn't compile in
same working library, or library add through library_clause and use_clause).

Be happy ;-)
JaI