How do you initialize signals in VHDL?

[Madhu]

Hello,
I understand that, initial values for signals are not supported for
synthesis. My problem is with the reset signal. For instance in the
below code,
***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example is
port (
clock: in STD_LOGIC;
enable: in std_logic;
datain: in STD_LOGIC;
dataout: out STD_LOGIC
);
end gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is
begin
if(rising_edge(clock)) then
if(reset='1') then
reset='0';
end if;
if(reset='0') then
if(enable ='0') then
dataout<='0';
end if;--enable
if(enable='1')then
dataout<=datain;
end if;--enable
end if;--reset
end if;--rising edge

end process;
end example_arch;

I expect "reset" signal to be high for just one clock cycle, at the
start of the process and after the first clock cycle "reset" to be low
through out the process. That can expect to work for simulation if I
initialize reset signal to 1.
signal reset:std_logic:='1';
But, it wouldn't help for synthesis. How can I tackle with this
situation ?

Thanks for your time…!!

 

[valentin tihomirov]

if RESET = '1' then
REG <= INIT;
elsif CLK'event and CLK = '1' then
REG <= REG_NEXT;
end if;

 

[Jim Lewis]

I expect "reset" signal to be high for just one clock cycle, at the

start of the process and after the first clock cycle "reset" to be low
through out the process. That can expect to work for simulation if I
initialize reset signal to 1.
signal reset:std_logic:='1';
But, it wouldn't help for synthesis. How can I tackle with this
situation ?

Reset needs to be an input to this block and generated
at one central source, typically outside your chip.
Typically reset will be active for several (100-1000) cycles
after power stabalizes. A simple reset circuit is RC.
There are also some chips.

With this, reset becomes a board issue, not one you will
generate separately inside each block.

Best Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Keith R. Williams]

Hello,
I understand that, initial values for signals are not supported for
synthesis. My problem is with the reset signal. For instance in the
below code,
***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example is
port (
clock: in STD_LOGIC;
enable: in std_logic;
datain: in STD_LOGIC;
dataout: out STD_LOGIC;

reset: in STD_LOGIC

You need a reset from somewhere else if you want to be guaranteed a
state on power up.

);
end gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is
begin
if(rising_edge(clock)) then
if(reset='1') then
reset='0';

I think you want to set dataout to 0, not reset. You cannot set

end if;

No end if. You want your process clocked, not just the reset.

if(reset='0') then
if(enable ='0') then
dataout<='0';
end if;--enable

You're saying that if reset and enable are inactive you want the output
to be '0'. I don't think that's what you want.

if(enable='1')then
dataout<=datain;
end if;--enable

You've now got a D latch (level sensitive) gated by not_reset and
enable. Actually you don't because if reset and enable are zero the
output is '0' (from above), so you have a strange gate. ...with an edge
triggered reset. ...not good.

end if;--reset
end if;--rising edge

end process;
end example_arch;

What you really want is more like:

***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example is
port (
clock: in STD_LOGIC;
enable: in std_logic;
datain: in STD_LOGIC;
dataout: out STD_LOGIC;
reset: in STD_LOGIC; -- <-- ADDED
);
end example; -- *NOT* gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is
begin
if(rising_edge(clock)) then
if(reset='1')
then -- synchronous reset
dataout <='0';
elsif(enable='1')
then
dataout<=datain;
end if;--reset
end if;--rising edge clock

end process;
end example_arch;

Or if you'd rather have an asynchronous reset:

***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example is
port (
clock: in STD_LOGIC;
enable: in std_logic;
datain: in STD_LOGIC;
dataout: out STD_LOGIC;
reset: in STD_LOGIC; -- <-- ADDED
);
end example; -- *NOT* gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is
begin
if reset = '1'
then -asynchronous reset
dataout <= '0'
elsif rising_edge(clock)
then
if(enable='1')
then
dataout<=datain;
end if;--enable
end if; --reset

end process;
end example_arch;

I expect "reset" signal to be high for just one clock cycle, at the
start of the process and after the first clock cycle "reset" to be low
through out the process. That can expect to work for simulation if I
initialize reset signal to 1.

Yes you have a synchronous reset (sorta), though it is reset on the
rising edge of the clock. You have some serious problems in this logic
though (see above).

signal reset:std_logic:='1';
But, it wouldn't help for synthesis. How can I tackle with this
situation ?

You build a testbench that hooks to the architecture at a higher level
(make this a component in your higher level implementation). You put
your simulation stuff in there and it doesn't get synthesized.

 

[Vinh Pham]

If your synthesis tool creates FFs that power up as zero, by default, then
you could try this:

process(clk)
begin
if rising_edge(clk) then
if reset_n = '0' then
reset_n <= '1';
end if;
end if;
end process;

reset <= not(reset_n);

 

[Ahmed Samieh]

If your synthesis tool creates FFs that power up as zero, by default, then
you could try this:
process(clk)
begin
if rising_edge(clk) then
if reset_n = '0' then
reset_n <= '1';
end if;
end if;
end process;
reset <= not(reset_n);

thanx Vinh Pham for this tip
i know the postes very old but i just wanna ask how to force the synthesis tool to create FFs powered up as 0's?
my synthesis tool is Precision RTL Synthesis from Mentor Graphics FPGA Advantage 7.2

 

[vbehravan]

Hello,
I understand that, initial values for signals are not supported for
synthesis. My problem is with the reset signal. For instance in the
below code,
***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example is
port (
clock: in STD_LOGIC;
enable: in std_logic;
datain: in STD_LOGIC;
dataout: out STD_LOGIC
);
end gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is
begin
if(rising_edge(clock)) then
if(reset='1') then
reset='0';
end if;
if(reset='0') then
if(enable ='0') then
dataout<='0';
end if;--enable
if(enable='1')then
dataout<=datain;
end if;--enable
end if;--reset
end if;--rising edge

end process;
end example_arch;

I expect "reset" signal to be high for just one clock cycle, at the
start of the process and after the first clock cycle "reset" to be low
through out the process. That can expect to work for simulation if I
initialize reset signal to 1.
signal reset:std_logic:='1';
But, it wouldn't help for synthesis. How can I tackle with this
situation ?

Thanks for your time…!!

don't worry about RESET signal for synthesis if your code works good in simulation. because RESET is an input signal and an external source will generate it in real world.
regards.

 

[dfriedman]

Can I specify an initialization value for a port input signal as a way of determining the state of the signal in the event it is left unconnected in the higher-level port map?

For example:

entity xyz is
port(
x : in std_logic := '1';
y : in std_logic := '0';
z : out std_logic
) end xyz;

architecture xyz_arch of xyz is
. . .
end xyz_arch;

---------

entity xyz_top is
. . .
) end xyz_top;
architecture xyztop_arch is
. . .
xyz1: entity work.xyz
port map (
x => x,
z => z
);
. . .
end xyz_top;

The idea is that if the port input signal y is not mapped, it should be given the default value '0' (effectively tied to ground) in the instance xyz1 of entity xyz. The question is, will this work for synthesis as well as simulation? Or do I always need to map y to a value, e.g.,

y => '0'

for synthesis purposes?