How to assign a hex or decimal value to a std_logic_vector of length19 bits?

G

gabor

I write almost exclusively Verilog code, but I inherited a
VHDL project and I need to make some changes to it.
I'm trying to make this human-readable, but I'm not
versed with VHDL, so I have no clue even what to look this up
under:

This code works, but it is not very readable:

signal flash_addr_i : std_logic_vector (18 downto 0) ;
.. . .
elsif ((flash_addr_i < 128) and write_flag = '1') then
-- How can a human being make sense of of this?
-- and why is 128 OK for the comparison above and not
-- for the assignment below?
flash_addr_i <= "0000000000010000000";
end if;
.. . .
I want to say:

flash_addr_i <= 128;

But then I get messages about flash_addr_i is not compatible with
with type of 128.

and if I try a hex constant like:

flash_addr_i <= x"00080";

I get bit width mis-match problems.

How can I write the equivalent of the Verilog:

flash_addr_i <= 19'd128;
or
flash_addr_i <= 19'h80;

I can't believe there's no way to do this in VHDL?

Stumped,

Gabor
 
K

KJ

I write almost exclusively Verilog code,

We won't hold that against you.
I want to say:

 flash_addr_i <= 128;

Since VHDL is a strongly typed language you are best viewing this as a
type conversion problem rather than a bit assignment problem. So the
conversion you want is from integer to std_logic_vector. This is a
two step conversion, one to convert from integer to a vector-o-bits
that has a specific numeric interpretation (i.e. type
ieee.numeric_std.unsigned) and then finally from that unsigned type to
a vector that is just a collection of arbitrary bits (i.e.
std_logic_vector). To do what you want then...

flash_addr_i <= std_logic_vector(to_unsigned(128,
flash_addr_i'length));

Or if you prefer hex notation for the constant
flash_addr_i <= std_logic_vector(to_unsigned(16#80#,
flash_addr_i'length));
I can't believe there's no way to do this in VHDL?
There is.

Kevin Jennings
 
B

beky4kr

Sadly, I doubt that. In gabor's code we see...


So it seems fair to assume that the poor devil is saddled
with old code that uses std_logic_unsigned instead of
numeric_std. CONV_STD_LOGIC_VECTOR is what he needs.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Here is an example:

library ieee;
use ieee.std_logic_1164.all;

use work.amba.all;
use STD.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;

use IEEE.std_logic_unsigned."+";

entity mon is
generic (
msg_on : boolean := TRUE;
my_name : STRING := "I ";
--stop_add: std_logic_vector(HAMAX-1 downto 0) := X"8ffffffc"
stop_add: std_logic_vector(31 downto 0) :=
"10001111111111111111111111111100"
);
port (

HRESETN : in std_logic;
HCLK : in std_logic;

HMASTER : in std_logic_vector(3 downto 0);
....
The code is part of a free AHB monitor:
The following will show a simple AHB monitor. The monitor can be
applied to any AHB bus to debug the activity of the bus.

The monitor is easily attached to an AHB interface....
http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html
 
G

gabor

Gabor,
signal   flash_addr_i            : std_logic_vector (18 downto 0) ;

In VHDL-2008 (standardized, but not necessarily implemented yet) you can do:
   flash_addr_i <= 19D"128";
   flash_addr_i <= 19h"80";

For now you are stuck with:
   flash_addr_i <= "000" & h"0080";

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis    SynthWorks VHDL Training    http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.

I tried the 2008 standard stuff. XST 10.1 doesn't support
that yet...

I guess I'll use Jonathan's suggestion of adding 128
to another constant vector. That works for XST, which
makes sense because everywhere in the code I see stuff
like:

flash_addr_i <= flash_addr_i + 1;

Adding an integer constant to a std_logic_vector.

Unfortunately the project is also full of case statements
with binary strings for the case values, which makes it
hard to read, too. However I'll get to those when I find
out that they're broken...

This should get me by until I convert the whole project
to Verilog. Usually that helps me to understand other
people's code anyway. I'm not ready to start messing
with libraries.

Thanks for all the replies,

Gabor
 
G

gabor

Gabor,> I tried the 2008 standard stuff.  XST 10.1 doesn't support

Did you try my other suggestion (it is not new stuff):
flash_addr_i <= "000" & h"0080";




Yes this is operator overloading.


Keep these a binary strings - unfortunately until vhdl-2008,
the case statements are intolerant of "&" and expressions.


Not a good thing if the rest of your project team is using VHDL.
Probably ought to invest in training instead.  VHDL is quite
simple once you get past the initial learning stuff.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis    SynthWorks VHDL Training    http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.

There is no project "team" at this company or in other words,
I am the team. This project was supposed to be a purchased
turn-key design, but the external contractors didn't finish it.
All of the in-house designs are Verilog and likely to stay so.

Thanks for all your help,

Gabor
 
Joined
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hexadecimal to std_logic_vector

Hello, someone help me please
I have a signal z receives in hexadecimal,and this signal have multi value,I want to convert to binary, I use this syntax for example, convert the value 15

D(7 DOWNTO 0) <= to_stdlogicvector(x"15");
but I what I want is to convert SEVERAL value for example, a signal b
I use it but it does not work

ARCHITECTURE exo OF hex IS
signal b : integer range 0 to 65535 ;
BEGIN
b <= (r*10/5) ;
D(7 DOWNTO 0) <= to_stdlogicvector(x"b");
END exo;

can someone help me
 

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