# How to assign a hex or decimal value to a std_logic_vector of length19 bits?

Discussion in 'VHDL' started by gabor, Dec 5, 2008.

1. ### gaborGuest

I write almost exclusively Verilog code, but I inherited a
VHDL project and I need to make some changes to it.
I'm trying to make this human-readable, but I'm not
versed with VHDL, so I have no clue even what to look this up
under:

This code works, but it is not very readable:

signal flash_addr_i : std_logic_vector (18 downto 0) ;
.. . .
elsif ((flash_addr_i < 128) and write_flag = '1') then
-- How can a human being make sense of of this?
-- and why is 128 OK for the comparison above and not
-- for the assignment below?
end if;
.. . .
I want to say:

with type of 128.

and if I try a hex constant like:

I get bit width mis-match problems.

How can I write the equivalent of the Verilog:

or

I can't believe there's no way to do this in VHDL?

Stumped,

Gabor

gabor, Dec 5, 2008

2. ### KJGuest

We won't hold that against you.
Since VHDL is a strongly typed language you are best viewing this as a
type conversion problem rather than a bit assignment problem. So the
conversion you want is from integer to std_logic_vector. This is a
two step conversion, one to convert from integer to a vector-o-bits
that has a specific numeric interpretation (i.e. type
ieee.numeric_std.unsigned) and then finally from that unsigned type to
a vector that is just a collection of arbitrary bits (i.e.
std_logic_vector). To do what you want then...

Or if you prefer hex notation for the constant
There is.

Kevin Jennings

KJ, Dec 5, 2008

3. ### beky4krGuest

Here is an example:

library ieee;
use ieee.std_logic_1164.all;

use work.amba.all;
use STD.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;

use IEEE.std_logic_unsigned."+";

entity mon is
generic (
msg_on : boolean := TRUE;
my_name : STRING := "I ";
--stop_add: std_logic_vector(HAMAX-1 downto 0) := X"8ffffffc"
"10001111111111111111111111111100"
);
port (

HRESETN : in std_logic;
HCLK : in std_logic;

HMASTER : in std_logic_vector(3 downto 0);
....
The code is part of a free AHB monitor:
The following will show a simple AHB monitor. The monitor can be
applied to any AHB bus to debug the activity of the bus.

The monitor is easily attached to an AHB interface....
http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html

beky4kr, Dec 5, 2008
4. ### gaborGuest

I tried the 2008 standard stuff. XST 10.1 doesn't support
that yet...

I guess I'll use Jonathan's suggestion of adding 128
to another constant vector. That works for XST, which
makes sense because everywhere in the code I see stuff
like:

Adding an integer constant to a std_logic_vector.

Unfortunately the project is also full of case statements
with binary strings for the case values, which makes it
hard to read, too. However I'll get to those when I find
out that they're broken...

This should get me by until I convert the whole project
to Verilog. Usually that helps me to understand other
people's code anyway. I'm not ready to start messing
with libraries.

Thanks for all the replies,

Gabor

gabor, Dec 5, 2008
5. ### gaborGuest

There is no project "team" at this company or in other words,
I am the team. This project was supposed to be a purchased
turn-key design, but the external contractors didn't finish it.
All of the in-house designs are Verilog and likely to stay so.

Gabor

gabor, Dec 5, 2008
6. ### KJGuest

Well what do you know, there is an 'I' in 'team' after all.

KJ

KJ, Dec 6, 2008
7. ### mahfoudh

Joined:
Oct 20, 2013
Messages:
1
0

I have a signal z receives in hexadecimal,and this signal have multi value,I want to convert to binary, I use this syntax for example, convert the value 15

D(7 DOWNTO 0) <= to_stdlogicvector(x"15");
but I what I want is to convert SEVERAL value for example, a signal b
I use it but it does not work

ARCHITECTURE exo OF hex IS
signal b : integer range 0 to 65535 ;
BEGIN
b <= (r*10/5) ;
D(7 DOWNTO 0) <= to_stdlogicvector(x"b");
END exo;

can someone help me

mahfoudh, Dec 30, 2013