how to duplicate a component

[yossi]

Hello,
I am having a problem with component duplication.
I would like to duplicate this 2 port maps in one command (loop,generate...)
I have 2 types of parametes that need an Index:
1.1bit from an std_logic_vector m0_piezo_lg_p(0)
2.a regular register (m0_hifu_hv_pw0).
Can somebody assist?

Many thanks






M0_pulser_block0: pulser
port map
(
clk_64m => clk_64m,
reset_n => reset_n,
piezo_p => m0_piezo_lg_p(0),
piezo_n => m0_piezo_lg_n(0),
fire_busy => m0_fire_busy(0),
fire_piezo_1clk_r => fire_piezo_1clk_r,
fire_piezo_1clk_f => fire_piezo_1clk_f,
hifu_cal_sel => hifu_cal_sel,
hifu_hv_pw => m0_hifu_hv_pw0,
cal_hv_pw => m0_cal_hv_pw0,
phase_delay => m0_phase_delay0,
stdn => stdn,
break_duration_reg => break_duration_reg
);

M0_pulser_block1: pulser
port map
(
clk_64m => clk_64m,
reset_n => reset_n,
piezo_p => m0_piezo_lg_p(1),
piezo_n => m0_piezo_lg_n(1),
fire_busy => m0_fire_busy(1),
fire_piezo_1clk_r => fire_piezo_1clk_r,
fire_piezo_1clk_f => fire_piezo_1clk_f,
hifu_cal_sel => hifu_cal_sel,
hifu_hv_pw => m0_hifu_hv_pw1,
cal_hv_pw => m0_cal_hv_pw1,
phase_delay => m0_phase_delay1
stdn => stdn,
break_duration_reg => break_duration_reg
);

 

[Tricky]

Hello,

I am having a problem with component duplication.

I would like to duplicate this 2 port maps in one command (loop,generate...)

I have 2 types of parametes that need an Index:

1.1bit from an std_logic_vector m0_piezo_lg_p(0)

2.a regular register (m0_hifu_hv_pw0).

Can somebody assist?



Many thanks













M0_pulser_block0: pulser

port map

(

clk_64m => clk_64m,

reset_n => reset_n,

piezo_p => m0_piezo_lg_p(0),

piezo_n => m0_piezo_lg_n(0),

fire_busy => m0_fire_busy(0),

fire_piezo_1clk_r => fire_piezo_1clk_r,

fire_piezo_1clk_f => fire_piezo_1clk_f,

hifu_cal_sel => hifu_cal_sel,

hifu_hv_pw => m0_hifu_hv_pw0,

cal_hv_pw => m0_cal_hv_pw0,

phase_delay => m0_phase_delay0,

stdn => stdn,

break_duration_reg => break_duration_reg

);



M0_pulser_block1: pulser

port map

(

clk_64m => clk_64m,

reset_n => reset_n,

piezo_p => m0_piezo_lg_p(1),

piezo_n => m0_piezo_lg_n(1),

fire_busy => m0_fire_busy(1),

fire_piezo_1clk_r => fire_piezo_1clk_r,

fire_piezo_1clk_f => fire_piezo_1clk_f,

hifu_cal_sel => hifu_cal_sel,

hifu_hv_pw => m0_hifu_hv_pw1,

cal_hv_pw => m0_cal_hv_pw1,

phase_delay => m0_phase_delay1

stdn => stdn,

break_duration_reg => break_duration_reg

);

Use generate loops:

entity_gen : for i in 0 to 1 generate
--you can add extra signals here if you want - they remain local to the generate
begin --only required if you have extra signals

--put instantiation here - use i to index into arrays

end generate entity_gen; --you must use a label.

 

[yossi]

Use generate loops:



entity_gen : for i in 0 to 1 generate

--you can add extra signals here if you want - they remain local to the generate

begin --only required if you have extra signals



--put instantiation here - use i to index into arrays



end generate entity_gen; --you must use a label.

MANY THANKS!!!

 

[yossi]

MANY THANKS!!!

Many thanks for you help.



I have One more question related to my design,

I have another component that has lots of registers (120 registers 8bit each).

In this case I can declare an Array in side this component.

my quaestion is:

can I drive it out of this component to the top level?



I was trying to do that with no success, how should I define this output?





ENTITY registers IS
PORT (



my_array ut -- .....??


);
END;

 

[Tricky]

Many thanks for you help.







I have One more question related to my design,



I have another component that has lots of registers (120 registers 8bit each).



In this case I can declare an Array in side this component.



my quaestion is:



can I drive it out of this component to the top level?







I was trying to do that with no success, how should I define this output?











ENTITY registers IS

PORT (







my_array ut -- .....??





);

END;

declare the array type in a package, then both the top entity and the component can access the array type.