How to generate a pyramid of shift registers..?

[moti]

Hi all,
My problem is as follows - i need to create the following pyramid alike
design.
in my declarative part i need to declare the following signals :


signal reg1 : std_logic ;
signal reg2 :std_logic_vector (1 downto 0);
signal reg3 :std_logic_vector (2 downto 0);
...
...
signal regN :std_logic_vector (N-2 downto 0);

afterwards I need to connect them as follows :


if rising_edge (clk) then

reg1 <= in1;
reg2(0) <= in2;
reg3(0) <= in3;
....
regN(0) <= inN;

reg2 (1) <= reg2 (0);
reg3 (2 downto 1) <= reg2 (1 downto 0);
....
....
regN (N-1 downto 1) <= reg2 (N-2 downto 0);

end if;

-- outputs --
out1 <= reg1;
out2 <= reg2 (1);
out3 <= reg3 (2);
....
....
outN <= regN (N-1);


It seems to be a job for a "generate loop" but I dont know how can I
declare N signals...?

I will appreciate any help.
Thanks, Moti.

 

[Pieter Hulshoff]

It seems to be a job for a "generate loop" but I dont know how can I
declare N signals...?

Why not use a 2 dimensional array of Nx(N-1), and let the compiler toss out
all the un-used registers?

Regards,

Pieter Hulshoff

 

[zingafriend]

I think this: reg2 (1) <= reg2 (0); must have been reg2(1) <= reg1; If
this is the logic you need, then the ouput is only the msb's of each of
the registers, but then each registers msb gets the previous registers
msb. that being the case then your output after the pipeline is filled
will be nothing other than delayed values of the in1 bits only. But for
that you just need a n bit shift register, not a pyramid of register as
you mention.

-Neo

 

[moti]

Pieter Hulshoff wrote:

Why not use a 2 dimensional array of Nx(N-1), and let the compiler toss out
all the un-used registers?

Pieter Hulshoff

It seems like a good idea - I was just looking for some more elegant
solution like a special generate for it to be more readable..
But it looks like I have no choise.

Thanks, Moti.

 

[Egbert Molenkamp]

It seems like a good idea - I was just looking for some more elegant
solution like a special generate for it to be more readable..
But it looks like I have no choise.

Thanks, Moti.

You have a choice. You can generate the length of the array IN a generate
statement.
See example beneath. The extra process with label FIRST is needed since my
synthesis tool does not like
"-1 downto 0" when I change the generate stament in:
pyramid_structure: for i in N-1 downto 0 generate

Egbert Molenkamp


library ieee;
use ieee.std_logic_1164.all;
entity pyramid is
generic (n : positive := 3);
port (a : in std_logic_vector(n-1 downto 0);
clk : in std_logic;
b : out std_logic_vector(n-1 downto 0));
end pyramid;

architecture structure of pyramid is
begin
pyramid_structure: for i in N-1 downto 1 generate
process(clk)
variable pyr : std_logic_vector(i downto 0);
begin
if rising_edge(clk) then
pyr(i downto 0) := pyr(i-1 downto 0) & a(i);
b(i)<= pyr(i);
end if;
end process;
end generate;

firstrocess(clk) -- needed because synthesis does not like "-1 downto
0".
begin
if rising_edge(clk) then
b(0)<=a(0);
end if;
end process;

end structure;

 

[moti]

Hi Egbert,
Thanks for the example.
I never used a "rising_edge process" inside of a generate statement -
I will check it out..

Regards, Moti