How to run a zero-delay simulation in a design with a RAM?

Discussion in 'VHDL' started by Kelvin, Sep 14, 2003.

  1. Kelvin

    Kelvin Guest

    Hi, All:

    When I generated the RAM model from the Fab's software, it contains all the
    timing delay and checks.
    After I put it into my chip and run gate-level simulation with
    +delay_mode_zero (and +delay_mode_unit also),
    the timing and checks become zero, but the outputs from the RAM is wrong.

    I need to perform a zero-delay simulation to get the switching activity,
    while my process library puts a delay of 1ns
    in every gate, so is there any way to surpress this gate-delay while allow
    the timing delay & checks in the RAM?

    My simulator is NCVerilog.

    Best Regards,
    Kelvin, Sep 14, 2003
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.