I need help for RAM coding In verilog

Discussion in 'VHDL' started by apssingh, Jan 11, 2006.

  1. apssingh

    apssingh Guest

    I wand document and and idea for ram coding and verification with
    timing cycles included.
    plz send it in verilog.
    apssingh, Jan 11, 2006
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  2. apssingh

    Ajeetha Guest

    Why not ask for that in comp.lang.verilog then? Also, a simple RAM
    will be:

    reg [31:0] ram [7:0];

    Timing etc. - why not refer to a standard data sheet?

    Ajeetha, Jan 11, 2006
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