I2C slave clock stretching

Discussion in 'VHDL' started by praveen.kantharajapura, Jun 10, 2005.

  1. Hi all,

    I am implementing a I2C slave. I am refering XAPP333 for my deisgn.
    But one of the "limitation" of that reference design from XILINX is
    that it does not support "clock stretching".

    Suppose we do not need clock stretching "SCL" will be taken as INPUT to
    my I2C slave block.But if i want Clock stretching the slave also will
    be driving the SCL low when required to keep the master on hold.In this
    case SCL will be an INOUT for my module.

    My question is how to go about this implementation(tristate buffers on
    SCL!!!).
    Waht i am planning to do is, i will pull the SCL line low whenever i
    want to stop the clock transition on SCL from master else i will drive
    a "Z" on SCL.

    please comment on this implementation.


    Regards,
    Praveen
     
    praveen.kantharajapura, Jun 10, 2005
    #1
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  2. praveen.kantharajapura

    raghurash Guest

    HI Praveen,
    I also feel the same.SCL pin for slave must be INOUT.When you want
    to inset wait states pull scl line to GND else "Z".

    scl_pin <= 'Z' when !wait else '0';
    scl_internal <= scl when !wait else '0';

    scl_pin - INOUT pin of slave. scl_internal is clock internal to slave.
    Even this might work in FPGA implementation.

    Please let me know once you implement.My mail id is .

    Cheers,
    Raghavendra.s
     
    raghurash, Jun 14, 2005
    #2
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