Initial value on ports

Discussion in 'VHDL' started by Marek Ponca, Aug 8, 2003.

  1. Marek Ponca

    Marek Ponca Guest


    is there some way how to define an initial value of an output in verilog

    ....something similar as initial value of a signal in VHDL:
    a : std_logic := '1';

    There is a need for mixed-signal simulation, to have defined digital
    initial values before the simulation starts. It would help the analog
    to define the initial conditions.

    Marek Ponca, Aug 8, 2003
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