Initial value on ports

Discussion in 'VHDL' started by Marek Ponca, Aug 8, 2003.

  1. Marek Ponca

    Marek Ponca Guest

    hi,

    is there some way how to define an initial value of an output in verilog
    ?

    ....something similar as initial value of a signal in VHDL:
    a : std_logic := '1';


    There is a need for mixed-signal simulation, to have defined digital
    initial values before the simulation starts. It would help the analog
    simulator
    to define the initial conditions.

    Thanks,
    Marek
     
    Marek Ponca, Aug 8, 2003
    #1
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.