Andre,
I assume you're inquiring about a design targeted to an FPGA.
In that case usually, you don't have to do anything special
to utilize I/O flip flops. You can write a general RTL sequential
statement in your source code, and the synthesizer will assign
an I/O flip flop if possible. Another way to do it is to explicity
include a hardware instantiation of an I/O flip flop in your source
code. But I hate to do that.
The only time that I have run into trouble is if I have multiple clock
domains, and nearly all pins are utilized. In this case, the mapper
has restrictions on clock routing between neighboring I/Os. I forget
the rule exactly, and it changes depending on the FPGA family you're
using. But it is something like -- every 8 neigboring I/Os must share
the same clock source (check your data sheet for the true
relationship).
Once you've synthesize your design, you can look at the summary report
to see if it used I/O flip flops. Here is an example using Synplicity.
--------------------
Resource Usage Report
Part: lfec20e-3
Register bits: 25 of 9728 (0%)
I/O cells: 19
Details:
CU2: 4
FD1P3AX: 8
GSR: 1
IB: 11
IFS1P3DX: 9
OB: 8
OFS1P3DX: 8
ORCALUT4: 8
VHI: 1
VLO: 1
Found clock MY_COUNTER|clk with period 10.00ns
------------------------------
The component "IFS1P3DX" is an input flip flop.
The component "OFS1P3DX" is an output flip flop.
Another way to tell is to look at the results of the mapper report.
Here's an example:
Design Summary
--------------
Number of warnings: 0
Number of errors: 0
Number of registers: 25
PFU registers: 8
PIO registers: 17
Number of SLICEs: 8 out of 9856 (0%)
SLICEs(logic): 8 out of 7392 (0%)
SLICEs(logic/RAM): 0 out of 2464 (0%)
As RAM: 0
As Logic: 0
-----------------------------------------------------
This example shows that 17 Primary I/O registers are utilized.
Hope this helps.
If you need more explicit help.
Send me your email, and I can mail you the
complete example, including source code, synthesis
results, and mapper results.
Regards
Gary
