interfacing verilog and vhdl

Discussion in 'VHDL' started by cka, Aug 27, 2004.

  1. cka

    cka Guest

    i have code written in verilog and want to download it onto an FPGA.
    the top level file with the port assignments is in VHDL. how can the
    keyword foreign in vhdl be used to instantiate the verilog module in
    can somebody give me an example on how to do this?
    thank you.
    cka, Aug 27, 2004
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  2. Hello:

    It depends the simulator you are using. But in most of them they provide a
    binary to generate a VHDL wrapper for the verilog module you can
    instantiate into your VHDL code. Then you compile all and works.


    Javier Castillo

    (cka) wrote in
    Javier Castillo, Aug 27, 2004
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  3. cka

    pablo aimar Guest

    just instantiate like this

    processor: kcpsm3
    port map( address => address,
    instruction => instruction,
    port_id => port_id,
    write_strobe => write_strobe,
    out_port => out_port,
    read_strobe => read_strobe,
    in_port => in_port,
    interrupt => interrupt,
    interrupt_ack => interrupt_ack,
    reset => '0',
    clk => clk);

    where kcpsm3 is a verilog module.

    pablo aimar, Sep 11, 2004
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