is function conv_std_logic_vector() synthesizable?

Discussion in 'VHDL' started by walala, Sep 5, 2003.

  1. walala

    walala Guest

    Dear all,

    As I need some type-cast from integer(my internal data format) to
    std_logic_vector(in order to pick a partial slice of the array and
    output, say, from bit 15 downto 8),

    I used conv_std_logic_vector() function,

    Now the simulation is passed, but what about synthesize?

    Is it synthesizable? And will it map to a very complex device that
    really do the conversion? Or the synthesizer will be smart enough to
    know that I just want a simple type-cast?

    Thanks a lot,

    -Walala
     
    walala, Sep 5, 2003
    #1
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  2. It is synthesizable and it takes no resources to convert from an integer
    to a std_logic_vector since it simply maps the bits.
     
    Marc Guardiani, Sep 6, 2003
    #2
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  3. Hi walala!

    All (correct-implemented) type conversions are synthesizable, because
    VHDL has different types, but a wire in reality does not. This means,
    types are helpful for the HDL-designer, but all types represent the same
    "wire".

    The only point you have to check is that both the simulation tool and
    the synthesis tool use the same VHDL libraries.

    -> conv_std_logic_vector() comes from std.logic.arith (AFAIK). Note,
    that there are different implementations of this library. It is not
    "standardisized".
    -> Take the library numeric.std instead. This library is standardisized.
    There you have to use

    signal s_sulv : std_ulogic_vector(bitwidth-1 downto 0);
    signal s_int : integer;

    s_sulv <= std_ulogic_vector( to_unsigned(s_int,bitwidth) );

    if you want to convert an integer to std_ulogic_vector.

    Ralf
     
    Ralf Hildebrandt, Sep 6, 2003
    #3
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