Is it me or quartus ?

[Fred Bartoli]

Hello,

I have the following code :



width = 128

architecture bhv of yy is
function Stop_Sense ( IsSigCell, StopNextCells : std_ulogic_vector(Width-1
downto 0);
CurrentCell : natural range 0 to Width-1;
LookAheadDepth : natural range 1 to 16
) return std_ulogic is
begin
L1:for i in 1 to LookAheadDepth - 1 loop
if (CurrentCell - i) >= 0 then
if StopNextCells(CurrentCell - i) = '1' then
return '1';
else
if IsSigCell(CurrentCell - i) = '1' then
exit;
end if;
end if;
end if;
end loop;
return '0';
end;

signal StopNextCells : std_ulogic_vector (Width-1 downto 0);
signal StopCell : std_ulogic_vector (Width-1 downto 0);
signal IsBoundaryCell : std_ulogic_vector (Width-1 downto 0);

begin
..
..

StopCells: for i in 0 to Width-1 generate
StopCell(i) <= Stop_Sense(IsBoundaryCell, StopNextCells, i, N1_max);
end generate;

..
..
end bhv;



The function returns '1' when the StopNextCells vector contains at least a
'1' after the CurrentCell position and before the CurrentCell+LookAheadDepth
position and the first '1' in the IsSigCell vector.

Works OK in simulation, but quartus synthesize this as a simple OR on the
next N1_max StopNextCells positions which is not the intended behaviour.

What am I doing wrong in the code ?

BTW, I have 2 of these entities, plus as much of 2 other kinds of this, so I
have the equivalent of 1024 of these functions. Is there a more efficient
way to pack the logic ?

 

[Mike Treseler]

Works OK in simulation, but quartus synthesize

this as a simple OR on the next N1_max StopNextCells
positions which is not the intended behaviour.

Synthesis will delete any logic not affected
by the top entity inputs.
What is driving IsSigCell?

-- Mike Treseler

 

[Fred Bartoli]

Synthesis will delete any logic not affected
by the top entity inputs.
What is driving IsSigCell?

Thanks Mike.
Yes the siggnals exists are affected and used in the design.

I was answered on c.a.f that it is a quartus bug and that it should be
corrected on the 5.0 release.

In this case a simple work around is to replace the exit with a return.
Unfortunately I have more complicated functions were this simple change
can't be done and this forces me write more tortured code.

The other bad thing is that such an elementary bug now makes me very
suspicious about the quality of the generated netlist, and I now have to
functionally check it again after fitting. Really weird.

 

[Mike Treseler]

Fred Bartoli wrote:

The other bad thing is that such an elementary bug now makes me very
suspicious about the quality of the generated netlist, and I now have to
functionally check it again after fitting. Really weird.

Quartus is the new kid on the synthesis block and
has seen fewer design cases than the more mature
synthesis tools. I agree that a synthesis
error with no warning is most disconcerting, and
that testing of these netlists is indicated.
However, when you consider the difference in cost,
a little bit of "do it yourself" QA might be worth
the time.


-- Mike Treseler