label Process

Discussion in 'VHDL' started by Ronny Hengst, Aug 14, 2003.

  1. Ronny Hengst

    Ronny Hengst Guest

    Hello

    Which features in debbuging tools may not be available when I don't label my
    processes, loops...

    Thanks

    Ronny
     
    Ronny Hengst, Aug 14, 2003
    #1
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  2. Without labels, you lose some compile-time errors, that become
    logical errors at simulation time.

    With labels you are debugging something specific like
    " label mismatch, line 142. "

    Without labels, you may be debugging bizarre sim behavior.


    -- Mike Treseler
     
    Mike Treseler, Aug 15, 2003
    #2
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