Make file ...........Help Please

Discussion in 'VHDL' started by MACEI'S, Jul 9, 2003.

  1. MACEI'S

    MACEI'S Guest

    Hi Fellows,

    How can I synthesize multiple file one by one using xilinx compiler in
    MAKEFILE script. I have done using only one file but when I enter
    multiple files in "VHDL= ....." field thenI get the following error.

    make: *** No rule to make target `VIR3.vhd,VIR3_1.vhd,VIR3_2.vhd

    Rgds

    MACEI
     
    MACEI'S, Jul 9, 2003
    #1
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  2. Well, you should definitely get the makefile hand book - it
    has to many options ...

    But, to summarize, you probably want something like this:

    VHDL=VIR3.vhd VIR3_1.vhd VIR3_2.vhd # no commas !

    $(VHDL):
    synthesis_command [email protected]

    replace "synthesis command" with the name of your synthesis tool.
    The "[email protected]" will be automatically replaced with the vhdl file names.

    Regards,
    rudi
     
    Rudolf Usselmann, Jul 10, 2003
    #2
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