Mathematical formula implementation

Discussion in 'VHDL' started by vhdl_newbie, Mar 14, 2013.

  1. vhdl_newbie

    vhdl_newbie Guest

    I am a beginner with learn VHDL and I need to implement a mathematical formula for a job interview.
    I have one day to solve this problem so if there is any good samaritan that could help me with this problem, I would really appreciate it.

    solve this formula for Y



    P = [0:63]
    K = [0:4]
    Y = [0:512]

    Have a nice day !
    vhdl_newbie, Mar 14, 2013
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  2. vhdl_newbie

    vhdl_newbie Guest

    *I am a beginner with VHDL (sorry)
    vhdl_newbie, Mar 14, 2013
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  3. vhdl_newbie

    Fredxx Guest

    That looks like 4 variables and a single equation linking them together.

    Have a great interview.
    Fredxx, Mar 14, 2013
  4. vhdl_newbie

    vhdl_newbie Guest

    Le jeudi 14 mars 2013 19:51:46 UTC-4, Fredxx a écrit :
    Thank you for your interest, the problem may be unclear but that is the wayit was written.
    I think they want me to design an architecture with 9 bits output (Y), 2 bits (K) input and 5 bits input (P)
    Do you have any idea of the functions I could use for product, division andeponentiation ?
    (I am new to VHDL)
    vhdl_newbie, Mar 15, 2013
  5. vhdl_newbie

    rickman Guest

    If this were a real requirement, I would say there was something wrong
    with it. It could be coded, but it would be hard to actually build. If
    P is a 64 bit integer, it has a range of 0 to 2^64-1. As an exponent of
    K, the result would have 2^64+4 bits. I don't know how to represent
    that in a way that VHDL would understand. Heck, my calculator threw up
    when I tried to calculate it.

    Are you sure this is the right question? I can't see any value in
    asking a job candidate such a question.

    WAIT! The notation is wonkey! You mean the variables have his range,
    not that many bits, right? That's different. But it still doesn't fit.
    You can't shove the result into the range for Y.

    Maybe that's what they want you to tell them?
    rickman, Mar 15, 2013
  6. Assuming [0:x] are ranges,

    p: natural range 0 TO 63;
    k: natural range 0 TO 4
    ) RETURN natural IS
    VARIABLE result: natural;
    result := (p**2 + k*p)/16;
    IF result > 512 THEN
    result := 512;
    END IF;
    RETURN result;

    Is this synthesizable? No idea, probably not, but it was not a requirement.
    And you!
    Paul Uiterlinden, Mar 15, 2013
  7. vhdl_newbie

    Fredxx Guest

    I would have treated P, K and Y as 64, 5 and 513 element arrays
    Fredxx, Mar 15, 2013
  8. vhdl_newbie

    Rob Gaddi Guest

    I think you're misreading. That's (P^P+K*P)/16, or P(P+K)/16
    Rob Gaddi, Mar 15, 2013
  9. vhdl_newbie

    rickman Guest

    Yes, you are right. I misread the problem. Wouldn't be the first time
    and won't be the last...

    But the problem remains. If those are ranges, the general result won't
    fit in the variable Y.
    rickman, Mar 15, 2013
  10. vhdl_newbie

    chrisabele Guest

    I think Rob's rewriting is really helpful (aside from his forgetting to
    change the ^ to a *). And if we assume that the values in [] are value
    ranges rather than bit index ranges then the maximum Y value would be
    63*(63+4)/16 = 264 which certainly is within the range [0:512]. Of
    course I've assumed that Y must be an integer and truncated (actually
    rounded) the result, plus the intermediate result is certainly much
    larger than 512. But given those assumptions the problem is not
    unreasonable. So perhaps the code that Paul posted is the best answer.

    Perhaps the point of the interview question was to see if the candidate
    would raise exactly the issues that have been discussed this thread...

    chrisabele, Mar 16, 2013
  11. vhdl_newbie

    rickman Guest

    Yes, I forgot to divide by 16, I was only looking at the multiplications.

    I still think it is a bit of an odd question for a job interview, but I
    suppose it must relate to something the company does, or maybe the
    interviewer just picked this as an example question without any real

    I had an interview once where the company president asked me about how I
    had solved a very tough problem before. Immediately a problem came to
    mind that I had done a couple of years before and had stumped me for a
    few days before coming up with a solution. Unfortunately I couldn't
    recall the solution! So much for thinking on your feet.

    Needless to say, I didn't get the job...
    rickman, Mar 16, 2013
  12. vhdl_newbie

    rickman Guest

    I've been thinking a bit about this and I would not advise that you go
    into the interview trying to give the impression that you "know" VHDL.
    You are clearly a beginner and that will show in the interview. What
    you should consider is trying to learn a bit about VHDL and let them
    know that you are coming up the learning curve.

    One of the big difficulties beginners have with VHDL is the strong
    typing. Learn how to convert between the different types, when you need
    to do what type of conversion and why. If you can explain all this in
    an interview I think it will impress anyone. If I were interviewing
    someone as a VHDL designer and they could articulate a good approach to
    type conversions I know I would be favorably impressed. I expect a lot
    of people here can't do that.
    rickman, Mar 16, 2013
  13. vhdl_newbie

    vhdl_newbie Guest

    Thanks a lot for all of you answer, it was pretty helpful for me. So, for those asking, I already did the interview. It was only afterwards that they asked me to solve a VHDL problem. Also, I think the [] was meant to be the range for the integers. So I came up with this, from your what I had the time to learn in one day. Don't bother correcting it, I had to send it quickly so it is too late to change it now. I send it in case it could interest someone.
    Thanks again for the help !

    library IEEE;
    use IEEE.Std_Logic_1164.all;
    use IEEE.Numeric_Std.all;

    entity formule is
    port (
    K : in Unsigned(2 downto 0); -- 3 bits for [0:4]
    P : in Unsigned(5 downto 0); -- 6 bits for [0:64]
    Y : out Unsigned(9 downto 0); -- 10 bits for [0:512]
    end formule;

    architecture arch of formule is

    -- refactorizing : Y=P*(P+K)/16

    Signal sum : Unsigned(6 downto 0); -- 7 bits for (P+K)
    Signal numerator : Unsigned(12 downto 0); -- 13 bits for P*(P+K)


    sum <= P + K;
    numerator <= P * sum;
    Y <= numerator srl 4; -- I shift the numbers 4 bits to the right to divide by 16 (someone told me "/" doesnt work all the time)

    end arch;
    vhdl_newbie, Mar 18, 2013
  14. vhdl_newbie

    rickman Guest

    I can't resist. This is pretty good, but you didn't allow enough range
    for P. It is 0 to 64, not 0 to 63. So you need 7 bits. sum still only
    needs 7 bits because the sum won't exceed this range given the input

    Otherwise this is good for a beginner.
    rickman, Mar 19, 2013
  15. vhdl_newbie

    Andy Guest

    Me neither (can't resist).

    Given the non-power-of two ranges involved, I would keep this in the integer domain:

    K: in natural range 0 to 4;
    P: in natural range 0 to 64;
    Y: out natural range 0 to 64 * (64 + 4) / 16; -- 9 bits is enough

    Y <= P * (P + K) / 16;

    Synthesis tools recognize a multiply/divide by a constant power of two as a shift operation anyway.

    Keep in mind, if you are trying to use built-in MAC blocks in an FPGA, this needs to be pipelined across multiple clock cycles. Otherwise a combinatorial implementation is going to be very slow and large.

    Andy, Mar 19, 2013
  16. vhdl_newbie

    vhdl_newbie Guest

    Thanks for the advices, Andy and Rick, i'll try the keep them in mind.
    Again, thanks a lot for your help, you are a great community !
    vhdl_newbie, Mar 22, 2013
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