Modelling real life components in VHDL

[Moikel]

Hey all,

I am undertaking a project in college to model a simple MC68008 system
using VHDL. We don't actually have to model the entire 68k processor,
but we have to fully implement and simulate many existing real life
components. These components are:

TMM2764AD EEPROM
R6551 Asynchronous Communications Adapter
HMM611P Static CMOS RAM

What I really need is for someone to point me in a good direction as
far as modelling these components is concerned. We've never done
anything like this before, so just some general information about
implementing real devices in VHDL would be great. Any books in
particular? Websites (yes, I did look, but I couldn't find anything)?

Thanks for all replies,

 

[Thomas Thorsen]

Hey all,

I am undertaking a project in college to model a simple MC68008 system
using VHDL. We don't actually have to model the entire 68k processor,
but we have to fully implement and simulate many existing real life
components. These components are:

TMM2764AD EEPROM
R6551 Asynchronous Communications Adapter
HMM611P Static CMOS RAM

What I really need is for someone to point me in a good direction as
far as modelling these components is concerned. We've never done
anything like this before, so just some general information about
implementing real devices in VHDL would be great. Any books in
particular? Websites (yes, I did look, but I couldn't find anything)?

Thanks for all replies,

VHDL is made for describing "real devices" (what other purpose is there??)

I can recommend the book "VHDL for logic synthesis" by Andrew Rushton as it
takes a very practical approach to VHDL.

-Thomas

 

[Moikel]

Oh maybe I wasn't very clear. What I meant to say was 'existing'
devices. I'm not designing my own devices, just modelling those that
already exist and are typically available from component suppliers etc.

 

[Ralf Hildebrandt]

but we have to fully implement and simulate many existing real life
components. These components are:

TMM2764AD EEPROM
R6551 Asynchronous Communications Adapter
HMM611P Static CMOS RAM

What I really need is for someone to point me in a good direction as
far as modelling these components is concerned.

Often the data sheet gives you information about the required I/O
behavior. If you model a box, that has the same behavior, you are done.
Ok, you additionally need the information, what these components do, but
I guess their ideal behavior should be known.

You could write a model of their ideal behavior and try to model their
real delays while modeling the I/O behavior.
Otherwise you could try to build a model that is as close as possible to
their real behavior. I guess this is more difficult.

Ralf

 

[backhus]

Hi Moikel,
have a look at this:

http://www.freemodelfoundry.com/VHDL_models.html

http://www.freemodelfoundry.com/welcome.html

have a nice simulation

Eilert

 

[Mark McDougall]

Oh maybe I wasn't very clear. What I meant to say was 'existing'
devices. I'm not designing my own devices, just modelling those that
already exist and are typically available from component suppliers etc.

Your best bet is to take some existing (free) models of similar devices
(EEPROM, SRAM) and their respective datasheets. Look at *what*
properties are being modelled as well as how - that should give you a
good indication of what you need to do for your own devices - no doubt
you'll be able to base it on the free models.

FWIW I'd start with the EEPROM, and finish with the R6551...

Regards,
Mark

 

[Brian Drummond]

Hey all,

I am undertaking a project in college to model a simple MC68008 system
using VHDL. We don't actually have to model the entire 68k processor,
but we have to fully implement and simulate many existing real life
components. These components are:

TMM2764AD EEPROM
R6551 Asynchronous Communications Adapter
HMM611P Static CMOS RAM

The SRAM should be easy - various manufacturers have memory models for
asynch RAM; Cypress among them; if you can't find a 6116? model, one of
these can probably be adapted; it probably only needs changes to delays
in the timing package. (Multiplying them all by about 10 for example!)

Again if you can't find the EPROM as a model, you can go a long way with
an SRAM model, pre-initialised from a file, ignoring the Write line.
Assuming you don't need to model reprogramming during operation.

Modelling the ACIA will be harder; I would concentrate on modelling its
bus interface to the CPU, and feeding its "communication" side to/from
files; unless you are also modelling the devices to which it is
connected. If you can find a related component (e.g. one which
implements the 6502 bus interface) that would make life simpler.

- Brian