ModelSim Error

Discussion in 'VHDL' started by u_stadler, Aug 8, 2005.

  1. u_stadler

    u_stadler Guest

    hi

    could somebody help me with this error message i get from model sim se?
    i'm trying to simulate (post place and route) my design and get the
    following error message:
    "error code: Failure: (vsim-3807) Types do not match between component
    and entity for port key_input"

    My signal key_input is a integer right now (normally it is my own data
    type but i changed it because i thought perhaps models sim can't handel
    that). if i change it to std_logic i can simulate.
    the behavioral simulation works just fine even with my datatype.
    i checked my design module and the test bench and the datatypes are the
    same in the entity and the component declaration.
    if it helps i can post the source.
    any ideas somebody?

    thanks
     
    u_stadler, Aug 8, 2005
    #1
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  2. u_stadler

    ALuPin Guest

    Yes, post the relevant part of your code.

    Rgds
    André
     
    ALuPin, Aug 8, 2005
    #2
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  3. u_stadler

    Andy Peters Guest

    An integer is not the same at all as a std_logic (do you really mean
    std_logic_vector?).

    Make sure the signal has the same type everywhere : in the test bench
    instance, in the component declaration, in the entity declaration.
    make sure you compile from the bottom up, and make sure you select the
    proper configuration (if applicable).

    -a
     
    Andy Peters, Aug 8, 2005
    #3
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