modelsim - looking at memories

Discussion in 'VHDL' started by fpgawizz, Apr 4, 2005.

  1. fpgawizz

    fpgawizz Guest

    Folks
    I was trying to look at an std_logic array in modelsim for a block ram
    module that i wrote.I can see the data and address lines wiggling with the
    correct test input data from my test bench.however if i see the internal
    RAM array all locations come up as "UUUUUUUU".Any ideas why this could be
    happening?

    thanks
     
    fpgawizz, Apr 4, 2005
    #1
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  2. Since a RAM has no reset,
    it comes filled with 'U's.
    Writing RAM will replace
    the 'U's at one location with data.

    -- Mike Treseler
     
    Mike Treseler, Apr 4, 2005
    #2
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  3. fpgawizz

    fpgawizz Guest

    Mike
    I am writing data into this RAM. I have a testbench that writes like 5
    data bytes into 5 different locations..I can see the addr and data lines
    getting the right data when WE is asserted but inside the array, they all
    turn up as "UUUUUUUU"
     
    fpgawizz, Apr 4, 2005
    #3
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