Multi Valued logic simulation using VHDL?

Discussion in 'VHDL' started by Guru Prasad, Feb 20, 2004.

  1. Guru Prasad

    Guru Prasad Guest

    Hi!

    I have taken on a project of benchmarking the relative performance of
    a binary ALU Vs a ternary ALU. I was wondering if I could use VHDL to
    program a simple ALU that does multiplication, addition and division
    for multi-valued logic and if so, could someone point me to recources
    where I can find more information about the same?

    thanks.
     
    Guru Prasad, Feb 20, 2004
    #1
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  2. Guru Prasad

    goouse99 Guest

    Am Samstag, 22. September 2012 23:55:43 UTC+2 schrieb ashw_pict:
    Hi,
    an intersting paper, since they provide the source code for their ternary types and operators.
    But one thing makes me wonder.
    To my understanding the ternary logic type should improve arithmetic functions.
    In the paper the ternary type uses {0, Z, 1}.
    So, when I get some logic result, is Z interpreted as 0.5?
    Why didn't they create a new type {0 1 2} and overload the operators and functions for it, just like it is done for the std_logic type?

    Have a nice simulation
    Eilert
     
    goouse99, Sep 28, 2012
    #2
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  3. Guru Prasad

    Lokesh Kanna Guest

    hai guru,
    I hv planned to do the same project that u did...Though u hv done years back,help me by sending some links where we can find the sample codes for ternary MVL operation. .

    thanks in advance...:)
     
    Lokesh Kanna, Jan 30, 2014
    #3
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