Multiplexer Index

[woko]

Hi! I have to design a FPGA with lots of registers read/writeable by a
cpu. So far I had only a few registers and for read access there was a
"case" multiplexer implemented. (see example case)

Because now I have around 60 registers there would be 60 entries in the
"case", I would like to have it indexed. As you can see I wrote a
simple index code (example index) which could be compiled by the xilinx
ise but I did not check both if they really work.

The thing is: the index method uses much less units in the fpga as the
case method. (case around 768 slices, index around 1004 slices)
Is there a way I can achieve the same usage of logic with case style?
I guess it could depend on the synthesize tool, but I don't want to
hear that because I won't get any other...

regards,

Wolfgang Kopp


example case:
pDatamux: process (sA, Pwm(0).Reg, Pwm(1).Reg, Pwm(2).Reg)
begin
case sA is
when X"4" => sDo <= Pwm(1).Reg;
when X"8" => sDo <= Pwm(2).Reg;
when others => sDo <= Pwm(0).Reg;
end case;
end process;


example index:
signal sDo :std_logic_vector (10 downto 0);
signal AIndex : integer range 0 to cREGISTER;
begin

Reg(0).Dout <= conv_std_logic_vector(cVersion, 11);

AIndex <= conv_integer((sAdr - cREG_BASE))/2;
sDo <= Reg(Aindex).Dout;

 

[Andy Peters]

Hi! I have to design a FPGA with lots of registers read/writeable by a
cpu. So far I had only a few registers and for read access there was a
"case" multiplexer implemented. (see example case)

Because now I have around 60 registers there would be 60 entries in the
"case", I would like to have it indexed. As you can see I wrote a
simple index code (example index) which could be compiled by the xilinx
ise but I did not check both if they really work.

The thing is: the index method uses much less units in the fpga as the
case method. (case around 768 slices, index around 1004 slices)
Is there a way I can achieve the same usage of logic with case style?
I guess it could depend on the synthesize tool, but I don't want to
hear that because I won't get any other...

I suppose you could implement your registers in RAMs, but that might
not be practical for your design if you need immediate access to all of
the registers all of the time.

-a

 

[woko]

I suppose you could implement your registers in RAMs, but that might

not be practical for your design if you need immediate access to all of
the registers all of the time.

-a

This would be a possible solution for some of the registers. I could
place the PWM compare values in the RAM and periodically query them in
between one PWM clock, which is just about 1us.
But I would like to keep it simple as long as I have enough distributed
RAM in my FPGA.
cheers,
Wolfgang Kopp