I don't think i understand.
If i don't put a default "tense"
I think the usual English word is "clause" - but no problem...
the value of the output remains the last output assigned, right?
Yes, and then the code would not be good for synthesis.
and the same if i assign ------ you say... mmm... even if i assign all Z i
think.. mmm ... so?
If you assign -----, you are telling the synthesis tool "please build
SOMETHING here, but I don't care what I get, so make it as
simple as possible". If you assign ZZZZZ, you are saying "please
float the outputs in this case" - and that is MUCH more difficult.
If you assign (for example) "1000000" then you have a fixed
"error flag" value that can be tested somewhere else in the system.
at this point i can simply take out the last else lol!
no, as I mentioned above, that would make the code BAD for
synthesis, because it would create latches.
Tell us about what your test bench is doing...
mmm no, theorically tha angle can be totally random..
I understand that you can feed any angle value into this logic, but
my question was this: Let's suppose (as an example) that your
angle values are 16 bits. That's an integer range -32768 to
+32767. On this scale, what integer value represents +pi?
Here are some possible choices that might make sense:
(1) +pi = 180 degrees: integer value = +180
(2) +pi = 3.142 radians: integer value = +3142
(3) +pi = half a circle: integer value = +32768
Case (3) is brilliantly simple: your 16-bit integer
range -32768 to +32767 now represents exactly
-pi to +pi and you NEVER need to do angle reduction!
But maybe you NEED to represent angles larger than +pi.
So, let's try another choice - again, only for an example:
(4) +pi = half a circle; max. range = +/-4 circles;
so we represent +pi using integer 32768/8 = 4096
Why is this a good idea? Because we can now reduce any
angle into a -pi..+pi range simply by throwing away the top
three bits of the integer value! The bottom 13 bits (12 downto 0)
provide the reduced angle, in the range -4096 to +4095, same as
-pi to (nearly) +pi.
WHATEVER you do, the algorithm for reducing an angle into the
range -pi to +pi is essentially the same as "remainder after
dividing by 2pi". Dividing, by any number, is difficult in hardware
*unless the number is an exact power of 2*. This is the reason
why my choices (3) and (4) are such a good idea.
However, MULTIPLICATION is rather easy in FPGA hardware
because (at least in Xilinx and Altera parts) you probably
have built-in integer multiplier logic available. So, it
is a very good idea to use a multiplier to re-scale all
your angle values so that pi is represented by an
exact power of 2. After that multiplication, reducing
the angle to the -pi..+pi range is very simple: just
throw away some high-order (most significant) bits.
Any other way of doing it will be much harder to code -
too hard for this discussion :-(
nice piece of code
little question for you, master
in std_logic_vector( - signed(BININ) ); the "std_logic_vector" is a kind of
cast?
Yes. It's called an "array type conversion". SIGNED and
STD_LOGIC_VECTOR are both defined in exactly the same way:
they are arrays of STD_LOGIC, indexed by integer. Given two
types that are "closely related" in this way, VHDL allows you to
convert from one to the other by using the type name as if it
was a conversion function. The bit pattern is copied without
modification. The "signed" is also the same kind of cast.
this solves me much problems!
Me too
another little question: in the other problem you told me do declare a
signal to be able to "sign" the value. Right?
here i see there is no signal, but you simpli sign the binin value.
So if in a process block i call a signed(constant) this constant is used as
a signed value?
That's paradise for me lol
Yes, but you must be careful with constants.
VHDL knows that BININ is a STD_LOGIC_VECTOR, and therefore
it can be converted to SIGNED as you saw. But what about this...
SIGNED("111") ???? -- ERROR
What is the data type of "111"? Is it STRING? BIT_VECTOR?
STD_LOGIC_VECTOR? It could be any of those. VHDL cannot
decide. So the expression is illegal. HOWEVER, "111" is also
a satisfactory way to write a SIGNED constant. So we can
tell VHDL that the constant is of SIGNED data type, using
the type qualification syntax I showed you before:
SIGNED'("111") -- note the added apostrophe '
Now there is NO type conversion taking place. We are telling
the compiler that it must try to understand the "111" constant
as a SIGNED constant. This is OK.
Come to italy for a beer lol
Well now... here's a better idea: Come to the south of England
for a Doulos VHDL training class, and we'll introduce you to the
wonderful beer from our local brewery here in Ringwood :-D
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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