null statements...

[Jluis]

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE? i TRIED TO PUT NULL AND OPEN SENTENCES, BUT MAXPLUS GET A
ERROR MESSAGES. i NEED TO SYNTHETIZED.
MY DESIGN REQUIREMENTS IS TO LEFT TOTALLY OPEN WHEN Ira =0.

ANY IDEAS.........
tHANKS IN ADVANCE
JLUIS
MEXICO


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY buff4_ir IS
PORT( Ira: IN std_logic;
inbuf4: IN std_logic_vector(2 DOWNTO 0);
outbuf4: OUT std_logic_vector(2 DOWNTO 0));
END buff4_ir;

ARCHITECTURE archbuff4_ir OF buff4_ir IS
BEGIN
PROCESS(Ira, inbuf4)
BEGIN
IF Ira = '1' then
outbuf4 <= inbuf4;
ELSE
outbuf4 <= null;
end if;
end process;
END archbuff4_ir;

 

[Tim Hubberstey]

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE?

No. Think hardware: null or open or disconected _IS_ high Z.

 

[Charles Bailey]

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE? i TRIED TO PUT NULL AND OPEN SENTENCES, BUT MAXPLUS GET A
ERROR MESSAGES. i NEED TO SYNTHETIZED.
MY DESIGN REQUIREMENTS IS TO LEFT TOTALLY OPEN WHEN Ira =0.

This requirement doesn't make sense. What is wrong with setting the
output to Z, high impedance?

ANY IDEAS.........
tHANKS IN ADVANCE
JLUIS
MEXICO


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY buff4_ir IS
PORT( Ira: IN std_logic;
inbuf4: IN std_logic_vector(2 DOWNTO 0);
outbuf4: OUT std_logic_vector(2 DOWNTO 0));
END buff4_ir;

ARCHITECTURE archbuff4_ir OF buff4_ir IS
BEGIN
PROCESS(Ira, inbuf4)
BEGIN
IF Ira = '1' then
outbuf4 <= inbuf4;
ELSE
outbuf4 <= null;

"null;" is a statement, not a value. Can't do this.

 

[Just an Illusion]

"null;" is a statement, not a value. Can't do this.

outbuf4 <= open;

Simply, not ?

JaI

 

[Jluis]

tHANKS VHDL GROUP i SOLVE D THE PROBLEM
THIS QUESTION WAS AS PART OF MY BUS CONTROL PROGRAM, SO I DONT USE "Z"
I JUST PUT A PROCESS INSIDE OF MY TOP DESIGN, AND THAT´S IT, SO INSIDE
OF THIS PROCESS I PUT SEVERAL IF´s snetence, like this:::

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY datapath2 IS
PORT(
);

END datapath2;



ARCHITECTURE archdatapath2 OF datapath2 IS
COMPONENT instreg
END COMPONENT;

COMPONENT regfile
END COMPONENT;

COMPONENT alu
END COMPONENT;

COMPONENT proc
END COMPONENT;

COMPONENT ccl
END COMPONENT;

COMPONENT MAR
END COMPONENT;


COMPONENT MBR
END COMPONENT;

COMPONENT DATA
END COMPONENT;


SIGNALSSSSSSSS buss: std_logic_vector(21 DOWNTO 0);
MORE SIGNALS............

BEGIN
PROCESS(Irdir, Irk, Rfb, RfaB, Rfa, AluC, PCout, memout, Ira, Irb)
BEGIN
--- THIS if´S SOLVE MY BUS CONTROL PROBLEM
IF Irdir='1' THEN
buss <= bussA;
END IF;

IF Irk='1' THEN
buss <= bussB;
END IF;

IF Rfb='1' THEN
buss <= bussD;
END IF;

IF RfaB='1' THEN
buss <= bussEalu;
END IF;

IF Rfa = '1' THEN
Awire <= bussEalu;
END IF;

IF AluC='1' THEN
buss <= bussF;
END IF;

IF PCout='1' THEN
buss <= bussG;
END IF;

IF memout='1' THEN
buss <= bussH;
END IF;

IF Ira='1' THEN
Rwirea <= Rawire;
END IF;

IF Irb='1' THEN
Rwireb <= Rbwire;
END IF;

END PROCESS;

U1: instreg PORT MAP();
U2: regfile PORT MAP();
U3: alu PORT MAP();
U4: proc PORT MAP();
U5: ccl PORT MAP();
U6: MAR PORT MAP();
U7: MBR PORT MAP();
U8: DATA PORT MAP();

END archdatapath2;