T
Tim Hubberstey
At the risk of being branded a netcop, please post your *implementation*
related questions in comp.arch.fpga rather than here. comp.lang.vhdl is
for questions about the VHDL language (and for lack of another group,
VHDL simulators).
Implementation related questions are those such as:
Why did the fitter/place&route tool do ...?
What is the best way to implement <something> in my FPGA?
etc.
comp.arch.fpga is a better forum for these questions and you are more
likely to get an answer. Just remember, VHDL stops at the synthesizer,
everything that happens after the initial parsing by the synthesizer is
implementation. If you are not sure which it is, by all means ask in
both groups but, please, think a bit before you choose.
related questions in comp.arch.fpga rather than here. comp.lang.vhdl is
for questions about the VHDL language (and for lack of another group,
VHDL simulators).
Implementation related questions are those such as:
Why did the fitter/place&route tool do ...?
What is the best way to implement <something> in my FPGA?
etc.
comp.arch.fpga is a better forum for these questions and you are more
likely to get an answer. Just remember, VHDL stops at the synthesizer,
everything that happens after the initial parsing by the synthesizer is
implementation. If you are not sure which it is, by all means ask in
both groups but, please, think a bit before you choose.