Port mapping to (SIGNAL_NAME'range=>'0')?

Discussion in 'VHDL' started by Ken Morrow, Jul 23, 2003.

  1. Ken Morrow

    Ken Morrow Guest

    I have just had to move to a later version of a synthesiser, and I have
    found that some code which syntesised fine on the earlier version, now
    produces errors due to the port mapping of my component.

    I have something like:-

    signal DATA(2 downto 1); --NOTE. This signal is downto 1, not downto 0.
    --The 2 downto 1 is because of an interface to a third party which
    --numbers its busses in such a way

    component SOME_COMPONENT
    WIDTH : positive := 8);
    X_BUS : std_logic_vector(WIDTH-1 downto 0);
    Y_BUS : std_logic_vector(WIDTH-1 downto 0);
    end component SOME_COMPONENT;
    generic map(
    WIDTH => DATA'length
    port map(
    X_BUS => DATA,
    Y_BUS => (DATA'range=>'0')

    This now gives an error on the line:-
    Y_BUS => (DATA'range=>'0')
    saying something like 2 is out of range 1 downto 0.

    Yet the line
    X_BUS => DATA
    which also maps a 1 downto 0 to a 2 downto 1 is fine.

    I have worked around this by using:-
    Y_BUS => (DATA'length-1 downto 0=>'0')

    but I was wondering if the error reportedwas because my VHDL was illegal,
    or because the synthesiser had incorrectly reported an error.

    Many Thanks,

    Ken Morrow.
    Ken Morrow, Jul 23, 2003
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  2. This should also work:-

    Y_BUS => (others => '0')
    It sounds like the synthesiser is to blame.

    What did your simulator say? Simulators usually follow the LRM
    exactly, whereas synthesisers seem to treat it as a set of loose

    Allan Herriman, Jul 24, 2003
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  3. Ken Morrow

    Jerold Green Guest

    It looks like a syntax error to me. What you are writing is basically:

    Y_BUS => (2 downto 1 => '0');

    but Y_BUS has the range 1 downto 0, so this must be wrong. The use of the
    'range attribute does not change the fact that this is a constant index
    range associated with Y_BUS, not DATA.

    In the other port mapping:
    X_BUS => DATA;
    both are arrays of the same length and type, so the assignment takes place
    by position, not index.
    Jerold Green, Jul 26, 2003
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