port mapping

[john]

Hello,

My multiplexer is not working well for some reason. Even If I keep its
selection pin equals
to '1' ( just selecting Address bus) . I am generating just one address
0000hex through it
and getting wrong data.

If I remove this multiplexer, I get the right data at same address
(0000hex).
I am also attaching the code....
Please Advice!
Thanks
John



M14: multiplexer port map
(sel_14bit_mux,"0000000000000000000",data_from_latch,Address_bus(18
downto 0));

Data_out_bus(13 downto 0) <= Data_Bus(13 downto 0);


Process ( State_A )

Begin

Case State_A is


When A1 =>
incr_B <= '1';
LBL <= '1';
UBL <= '1';
sel_14bit_mux<= '1';

nextstate_A <= A2;

When A2 =>

incr_B <='0';
LBL <='0';
UBL <='0';
sel_14bit_mux <='1';


nextstate_A <=A1;



When others =>

nextstate_A <= A0;
End Case;
End Process;


-- DPR Process
Process ( DPR_CLK)

Begin


If (DPR_CLK 'event And DPR_CLK = '1') Then

State <= nextstate;
State_A <= nextstate_A;

End If;

End Process;

End DPR_ARCH;


-- Multiplexer

Entity multiplexer is

Port (

Sel_line : in std_logic;
data_in_counter :in unsigned ( 18 downto 0);
data_in_data_bus :in unsigned ( 18 downto 0);
data_out_mux : inout unsigned ( 18 downto 0)
);

End multiplexer;


Architecture muxq of multiplexer is

Begin


Process ( Sel_line )
Begin
Case Sel_line is

When '1' =>
data_out_mux <= data_in_counter;
When '0' =>
data_out_mux <= data_in_data_bus;
When others =>
nULL;
End case;


End process;

End muxq;

 

[Nicolas Matringe]

john a écrit:

Hello,

My multiplexer is not working well for some reason. Even If I keep its
selection pin equals
to '1' ( just selecting Address bus) . I am generating just one address
0000hex through it
and getting wrong data. [...]
Process (Sel_line)
Begin
Case Sel_line is
When '1' =>
data_out_mux <= data_in_counter;
When '0' =>
data_out_mux <= data_in_data_bus;
When others =>
nULL;
End case;
End process;

You should add data_in_counter and data_in_data_bus to your process
sensitivity list.
Actually, you don't need a separate entity and a process, just write
address_bus <= data_from_latch when sel_14bit_mux = '0' else (others =>
'0');
instead of your component instantiation. Keep it simple, it will be much
more readable.