Bar said:
Do we need to do POST Place and Route simulation to verify the asic before
production ?
Usually you need back annotated simulations. STA is used for most of the
timing checking, but few gate level simulations can tell if there were
some errors in the STA setup, or some test logic/clocking structures are
inserted incorrectly.
Usually ASIC flows also require post p&r simulations for all the test
vectors. The vendor will not manufacture the chip if the test vectors
are not good enough.
Use the testbench, include the netlist, backannotate the sdf, add delays
to external connections, chase all X propagations away, simulate, figure
out why there are warnings etc. Especially the X-hunting can be very
challenging in some designs.
This is something that will fail almost certainly if you don't have
access to someone who has done this before. Getting gate level
simulations up on a asic is a huge task, and requires good knowledge
of the design, ability to read schematics, familiarity with timing
and the simulator. It's quite normal to find at least one bug somewhere
in the simulator during the simulations
Fortunately I'm not the one paying your NRE, if you are asking how asic
should be verified at the late stages of the flow.
--Kim
