process runs 1 clock cycle behind rest of code

[MNQ]

Hello All

I have a process where the case statement is inside an if-then statement.
this process runs one clock cycle behind the rest of the code. Am I correct
in thinking that this process requires two clock cycles to start-up?

Thanks

Naveed

 

[Mario Trams]

Hello All

I have a process where the case statement is inside an if-then statement.
this process runs one clock cycle behind the rest of the code. Am I
correct in thinking that this process requires two clock cycles to
start-up?

No.

Bye,
Mario

 

[Allan Herriman]

Hello All

I have a process where the case statement is inside an if-then statement.
this process runs one clock cycle behind the rest of the code. Am I correct
in thinking that this process requires two clock cycles to start-up?

Check for delta races, which can be caused by having multiple clock
signals, e.g. clk1 and clk2, and you have a signal assignment
somewhere that looks like this:

clk2 <= clk1;

which makes clk2 lag clk1 by 1 delta cycle. The two clocks look the
same in your waveform viewer, but there is a difference.

Regards,
Allan.

 

[Jon]

Hi Naveed,
It would help to post an outline of the VHDL code. Are you sure
that in the if condition you are not using a registered version for
comparison vs. using the signal directly? There could be other
possible causes but without more information it is hard to say.

Jon