[Q] transaction

[csosz33]

Hi,

Here is the following design. I think at first when all process run
once there will be a new transaction
for "c" for "11 ns" because at the beginning internal=0. When a and b
evaluated to 1 a new transaction
generated for "c" for "7 ns". In this case this new transaction will
clear the previous
(that is for "11 ns")? I run it in a simulator and c is 1 in the 7-61
ns interval.


Thanks
Attila




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ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT( a, b : IN BIT; c : OUT BIT);
END AND2;

ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = '1'
ELSE internal AFTER (fall + (load * 3 ns));
END load_dependent;

entity and2_2_tb is
end and2_2_tb;

architecture TB_ARCHITECTURE of and2_2_tb is
component and2
generic(rise, fall : TIME; load : INTEGER);
port( a : in BIT; b : in BIT; c : out BIT );
end component;

signal a : BIT;
signal b : BIT;
signal c : BIT;
begin

UUT : and2
generic map ( rise=>5 ns, fall=>8 ns, load=>1 )
port map ( a => a, b => b, c => c );

STIMULUS: process
begin
a <= '1';
b <= '1';
wait for 50 ns;

a <= '1';
b <= '0';
wait;
end process;

end TB_ARCHITECTURE;
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