Question: inout signal assignment

Discussion in 'VHDL' started by John Potter, Sep 6, 2003.

  1. John Potter

    John Potter Guest

    Hello, I have a inout signal assignment problem.
    I can't assign a value to a inout signal which is a vector. I get
    "UUUUUUU" everytime.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity Testing is
    Port ( CLK: in std_logic;
    A : inout std_logic_vector(7 downto 0);
    B : inout std_logic_vector(7 downto 0);
    C : inout std_logic_vector(7 downto 0));
    end Testing;

    architecture Behavioral of Testing is


    bbbb: process is

    wait on CLK until CLK = '0';

    B <= A;
    B <= "11111111" after 50ps;
    B <= C after 80ps;

    end process bbbb;

    aaaa: process is

    A <= "10101011" after 0ns;
    C <= "00000000" after 10ps;

    end process aaaa;

    end Behavioral;

    A, B, C should behave like this:

    A = "10101011" 0ps
    B = "UUUUUUUU" 0ps, "11111111" 50ps, "0000000" 80ps
    C = "00000000" 10ps

    But I just get "UUUUUUUU" for B. My result:

    Anybody know why I got this result? If I delete line - "B <= C after
    80ps;" the final result is correct.

    John Potter, Sep 6, 2003
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  2. multiple inertial delay assignments to the same signal in the same
    simulation cycle: the last one overrides the others (it's a bit more
    complex but let's start with this). What you'll get is B = (others=>'U')
    until the first falling edge of CLK and then B = the value of C at first
    falling edge of CLK.
    As the first (and only) falling edge of CLK occurs at t=0ps the 3
    assignements of your bbbb process are all executed at t=0ps and B is
    assigned the value of C at 0ps, that is, (others=>'U').
    Tell us what behaviour you need and we'll give you a solution or two.

    Renaud Pacalet, Sep 8, 2003
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