Re: binary to BCD assistance

Discussion in 'VHDL' started by Glen Herrmannsfeldt, Jul 30, 2003.

  1. The attachment didn't come through. Can you just include some of the code
    in the body, instead of an attachment?

    -- glen
     
    Glen Herrmannsfeldt, Jul 30, 2003
    #1
    1. Advertisements

  2. OK, it did come through but I was looking in the wrong place. Still, it is
    often easier just to include it.

    I am much better at reading verilog than VHDL, but it doesn't look right to
    me. Though I think I don't understand the algorithm, I think it needs to be
    more complicated than that, though if you do an iterative algorithm it might
    not be so hard. How many clock cycles does it take to get the data from
    input to output? How many different values did you put through the
    simulator in testing?

    -- glen
     
    Glen Herrmannsfeldt, Jul 30, 2003
    #2
    1. Advertisements

  3. As I said, I read Verilog much better than VHDL. I didn't even notice the
    loop yesterday, which is why I didn't think it was complicated enough. OK,
    thought for today:



    (snip)
    Does the following generate a gated clock?
    The following statement must be done before the rest. While simulators may
    execute them in order, synthesized logic tends to execute them all at the
    same time.
    Does this generate a gated clock? Can you do it in traditional synchronous
    logic form, where either the previous contents, or the contents with "0011"
    added are loaded back in? (Also with the shift_en_s enable.)
    (snip)

    Gated clocks are especially hard in FPGA's.

    -- glen
     
    Glen Herrmannsfeldt, Jul 31, 2003
    #3
  4. Not if it follows the line

    elsif rising_edge(clk) then

    in a synchronous process.

    It's the process template that
    gives you a synchronous clock, not
    any single sequential statement.
    Actually, the synth will give you a netlist that simulates
    the same as that code, executed in order.

    Sequential statements execute in zero sim time.
    The only delay is for rising_edge(clk).

    Your code is a hardware specification that can only
    be completely understood in the context of simulation. There is
    usually no one-to-one correspondence between code statements
    and the synthesis netlist components.
    This synthesizes nothing unless bcd_value is assigned
    directly or indirectly to an entity port.

    If this assignment occurs within a synchronous process,
    the output will be registered by clk.
    If you stick to the synchronous process template, you
    will never have one to worry about.

    -- Mike Treseler
     
    Mike Treseler, Jul 31, 2003
    #4
  5. Glen Herrmannsfeldt

    FE Guest

    Hi Jason,
    I found your algorithm in C (see source after the vhdl code) on the net.
    It's cool.
    I rewrited your code like this (see bellow) and it works fine (I tested):
    (bin and bcd width (20 and 24) could be replaced by constants (C_BIN_WIDTH,
    C_BCD_WIDTH)).
    Hope this will help.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity bin2bcd is
    port(
    i_clk : in std_logic;
    i_rst_an : in std_logic;
    i_load_data : in std_logic;
    i_data : in std_logic_vector(20-1 downto 0);

    o_data_rdy_q : out std_logic;
    o_data_q : out std_logic_vector(24-1 downto 0)
    );
    end bin2bcd;

    architecture rtl of bin2bcd is
    begin
    --------------------------------------------------------------------------
    ----
    -- register mapping:
    --
    -- ------------------------
    -- | v_bcd_bin_q |
    -- ------------------------
    -- | av_bcd_q | |
    -- ------------------------
    -- | | av_bin_q |
    -- ------------------------
    -- |xxx| 3 bits overlaps to save 3 clk cycle processing and 3
    dff
    --
    --------------------------------------------------------------------------
    ----
    ps_bin2bcd : process (i_rst_an, i_clk)
    variable v_cnt_q : integer range 0 to 17;
    variable v_en_shift_q : std_logic;
    variable v_data_rdy_q : std_logic;
    variable v_bcd_bin_q : unsigned(20+24-3-1 downto 0);
    alias av_bin_q : unsigned(20-1 downto 0) is v_bcd_bin_q(20-1 downto 0);
    alias av_bcd_q : unsigned(24-1 downto 0) is v_bcd_bin_q(20+24-3-1 downto
    20-3);
    begin
    if i_rst_an = '0' then
    v_cnt_q := 0;
    v_en_shift_q := '0';
    v_bcd_bin_q := (others => '0');
    v_data_rdy_q := '0';
    elsif rising_edge(i_clk) then
    if i_load_data = '1' then
    av_bcd_q := (others => '0');
    av_bin_q := unsigned(i_data);
    v_cnt_q := 0;
    v_en_shift_q := '1';
    v_data_rdy_q := '0';
    elsif v_cnt_q = 17 then
    v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
    v_cnt_q := v_cnt_q; -- optional assignment
    v_en_shift_q := '0';
    v_data_rdy_q := '1';
    elsif v_en_shift_q = '1' then
    for i in 0 to 5 loop
    if av_bcd_q(4*i+3 downto 4*i) >= 5 then
    av_bcd_q(4*i+3 downto 4*i) := av_bcd_q(4*i+3 downto 4*i) + 3;
    end if;
    end loop;
    v_bcd_bin_q := v_bcd_bin_q sll 1;
    v_cnt_q := v_cnt_q + 1;
    v_en_shift_q := v_en_shift_q; -- optional assignment
    v_data_rdy_q := v_data_rdy_q; -- optional assignment
    else
    v_bcd_bin_q := v_bcd_bin_q; -- optional assignment
    v_cnt_q := v_cnt_q; -- optional assignment
    v_en_shift_q := v_en_shift_q; -- optional assignment
    v_data_rdy_q := v_data_rdy_q; -- optional assignment
    end if;
    end if;
    o_data_q <= std_logic_vector(av_bcd_q);
    o_data_rdy_q <= v_data_rdy_q;
    end process;

    end rtl;


    **********C source code************

    #include <stdio.h>
    #include <stdlib.h>
    #include <conio.h>

    #define BIN_SIZE 4
    #define MSB_MASK 0x80000000L
    #define BCD_SIZE 13

    typedef unsigned long BIN;
    typedef unsigned char BCD[BCD_SIZE];

    main()
    {
    BIN bin1,bin;
    BCD bcd;
    int i,j,k,carry;
    char temp[9];


    printf("enter number:");
    scanf("%lu", &bin1);
    bin=bin1;

    for (i=0; i<= BCD_SIZE; i++) bcd=0;
    printf("\n BCD BIN\n");
    for (i=0; i<8*BIN_SIZE; i++) {
    /* check for overflow */
    for (j=0; j<BCD_SIZE; j++) {
    if (bcd[j] >= 5) {
    bcd[j] += 3;
    /* printout for checking */
    for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
    printf(" %x\n", bin);
    }
    }
    /* shift right */
    carry = (bin & MSB_MASK) == MSB_MASK;
    bin = bin << 1;
    for (j=0; j<BCD_SIZE; j++) {
    bcd[j] = (bcd[j] << 1) | carry;
    carry = (bcd[j] & 0x10) == 0x10;
    bcd[j] = bcd[j] & 0xF;
    }
    /* printout for checking */
    for (k=BCD_SIZE; k--; ) printf("%4s ", itoa(bcd[k],temp,2));
    printf(" %x\n", bin);
    }
    printf("BIN = %lu\n", bin1);
    printf("BCD = ");
    for (k=BCD_SIZE; k--; ) printf("%d", bcd[k]);
    }

    regards
    FE
     
    FE, Aug 1, 2003
    #5
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.