Re: CAN controller VHDL code

[hamed]

opencores.org has a finished CAN controller project. Though I don't
know whether it works and/or supports all modes it may be a good
starting point. But if you insist building your own code, why don't
you download the CAN specification and build your own controller
from scratch?

best regards,

Markus Sponsel

========================================
profichip GmbH
Einsteinstraße 6
91074 Herzogenaurach
Germany

============================================
Thanks for your attention Markus.The CAN code you mentioned is
written by
Mr Shehrayar Shahin and he has send it to me via emial.But it is not
tested yet and it is not so readable for me( I can't understand the
characteristics of CAN by studing this code ).I have downloaded the
CAN specification ( CANA and CANB ) and I have studied them but still
some properties of CAN are not obvious for me.( For example I have
some questions about Error handling and synchronization of nodes
).That's why I need some thing more usefull and reliable.( A correct
and reliable code or an article which describes CAN in more details )

best regards

Hamed pishvayazdi

 

[Jonathan Bromley]

Thanks for your attention Markus. [...]
That's why I need some thing more usefull and reliable.( A correct
and reliable code or an article which describes CAN in more details )

Take a look at http://www.mjschofield.com/. It will be much
more helpful than trying to understand a CANbus core.

I agree that the error management in CAN is complicated,
but you are wrong if you complain that it's not CLEAR from
the spec - it is very clearly specified indeed. Sorry
to bring bad news, but you've simply got to go away and
sit in a quiet corner somewhere and read the spec carefully
until you understand it.

Good luck
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Thanks for your attention Markus.The CAN code you mentioned is
written by
Mr Shehrayar Shahin and he has send it to me via emial.But it is not
tested yet and it is not so readable for me( I can't understand the
characteristics of CAN by studing this code ).

No matter how well written core code is,
I can only completely understand a non-trivial
synth entity with the help of simulation waveforms.

Compile and Run the testbench, study the transactions,
then read the spec.

-- Mike Treseler

 

[shajeel]

hi,

could you plese get me VHDL code for CAN controller with supporting documents. i tried in opencores.org but it was in verilog HDL.
please send me the link or code to (e-mail address removed) or (e-mail address removed)

thankz in advance

regs
shajeel

 

[jgauthier68]

Simulation CAN Opencore Verilog

Hi!

I'm a little bit in the same situation. I've downloaded the CAN Bus opencore in Verilog format but I encounter some difficulties to simulate the core with ModelSim Altera web edition.

As soon as I want to simulate my testbench with "vsim" command, Modelsim says:


** Error: (vsim-3033) D:/00 - Harware Project/can/rtl/verilog/can_fifo.v(291): Instantiation of 'lpm_ram_dp' failed. The design unit was not found.
# Region: /can_testbench/i_can_top2/i_can_bsp/i_can_fifo
# Searched libraries:
# work

So, it seems to search the "work" library but if I type "vlib work", I see this message:

# ** Warning: (vlib-34) Library already exists at "work".

Where is the problem?! I really need to simulate the code to help me to understand how it work!!!

Thanks in advance!

 

[priyankasri_1]

help me with VHDL code for CAN controller

[FONT=[/I][/B][/B]]hi!!
i m a b.tech final year student working on project CAN controller can u send me the VHDL codes for CAN controller
regards
srivapriyanka










[/FONT]

"Markus Sponsel" <[email protected]> wrote in message news:<[email protected]>...
> hamed wrote:
> > Hi.Can anynoe help me to find a correct VHDL code for CAN DataLink
> > layer? I want it as a guide to write my own code.(It is not for
> > commercial use) Thanks&bye
>
> opencores.org has a finished CAN controller project. Though I don't
> know whether it works and/or supports all modes it may be a good
> starting point. But if you insist building your own code, why don't
> you download the CAN specification and build your own controller
> from scratch?
>
> best regards,
>
> Markus Sponsel
>
> ========================================
> profichip GmbH
> Einsteinstraße 6
> 91074 Herzogenaurach
> Germany
============================================
Thanks for your attention Markus.The CAN code you mentioned is
written by
Mr Shehrayar Shahin and he has send it to me via emial.But it is not
tested yet and it is not so readable for me( I can't understand the
characteristics of CAN by studing this code ).I have downloaded the
CAN specification ( CANA and CANB ) and I have studied them but still
some properties of CAN are not obvious for me.( For example I have
some questions about Error handling and synchronization of nodes
).That's why I need some thing more usefull and reliable.( A correct
and reliable code or an article which describes CAN in more details )

best regards

Hamed pishvayazdi