I hope I'm posting it in the right groups. I've been designing for a\nwhile, but with minimal JTAG knowledge.\n\nQ: Can I use JTAG interface to verify what I wrote into the SRAM,\ninstead of the traditional\nread-back method?\n\nMy setup and the reason for wanting to do it this way is :\nAn FPGA interfaces to a sync SRAM (QDR with separate write/read port).\nThe FPGA can write to the SRAM\nusing the processor interface, but does not have the read-back\ncapability, because the read port from the SRAM goes elsewhere (no\nread-back capability there, either). Why do it this way? So that the\neach of the write/read data bus is point-to-point, without stubs on the\nboard (150+Mhz). I could therotically bring the read bus back into the\nFPGA, then send it out again, but I'm fairly pin-limited. There are\nseveral SRAM interfaces, so whatever I do for each SRAM gets multipled\nby N. So, what I'd like to do is load the SRAM in a conventional\nmanner, then test it via the JTAG interface. The amount of time it\ntakes to verify doesn't matter.\n\nThe SRAM I'm thinking of using is Cypress, will be running it at\n150+Mhz, and the device supports these JTAG instructions : EXTEST,\nIDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported,\nactually). Looking at this, it looks like I need to use the FPGA to\nsupply the read controls at a slower rate, to match JTAG speed, then use\nSAMPLE instruction. Or, am I way off base here? Would it get too messy\nand should I just provite the read-back path at the cost of higher\npincount?\n\nThank you in advance for any input/suggestion.\n\nTo reply via email, change 'hard' to 'easy'.