Reset asynchronous assertion synchronous deassertion

[arant]

Hi Eveyone,

The specifications goes something like this :

The device core asserts reset to the device peripherals asynchronously
and releases (deasserts) the reset synchronously after 4 clock periods

there are two possible implementations for the above spec which one is
better :

signal reset_reg : std_logic_vector(3 downto 0);

p_reset_reg : process(clk,reset_async)
begin
if (reset_async = '0') then
-- on async reset assertion reset the registers
reset_reg <= (others => '0');

elsif (clk'event and clk = '1') then

reset_reg(0) <= '1';

reset_shift_reg : for i in (reset_reg'LOW to reset_reg'HIGH -1) loop
reset_reg(i+1) <= reset_reg(i);
end loop reset_shift_reg;

end if ;
end process p_reset_reg;

-- implementation 1 direct assignment of register value to reset_out

reset_out <= reset_reg(3);

-- implementation 2 assignment of decoded value of the register
-- bank to the reset out only when all the four registers attain
-- '1' then release reset to the device

reset_out <= reset_reg(0) and reset_reg(1) and reset_reg(2) and
reset_reg(3);

"I think the second implementation reduces the problem of metastability
at the reset_out as it is less probable that ll the four flops go
metastable at the same time"

Is the above statement (" I think ... time") valid

awaiting your replies

 

[KJ]

"I think the second implementation reduces the problem of metastability
at the reset_out as it is less probable that ll the four flops go
metastable at the same time"

Is the above statement (" I think ... time") valid

Not really. The probability of metastability on the last flip flop
decreases monotonically (and quite quickly I might add) as you make
your shift chain longer. So by basing logic on flip flops closer to
the begining of the chain you're actually increasing the chances that
your four clock cycle signal will have problems related to
metastability.

The flaw in your reasoning is that the outputs of each individual flip
flop is some random event that is either somewhat or totally
uncorrelated to the output of any other flip flops in the chain. If
this actually were the case then combining the four should give you an
overall better chance at getting a good signal. In reality, there is
near perfect correlation. For example, in order for flip flop #2
output to be metastable, flip flop #1 must have gone metastable and
remained that way for a long enough period of time to cause #2 to also
go metastable. However, there is absolutely no chance of #2 going
metastable if #1 has not.

Since the probability of metastability of a particular flip flop in the
chain is highly correlated with the probability of the previous flip
flop in the chain then using that previous flip flop is not providing
'new' information in the statistical sense and as I said in the first
paragraph is making things worse by using 'worse' information.

KJ