SDF generation

[neelesh]

Hi i have a doubt, In FPGA design
Can SDF file be generated after synthesis, if it can, can we see the
delays in the output result using that SDF file. If it can be generated
then which tools support generation after synthesis. As per my knowledge
SDF files are generated only after P&R.

Thanks and Regards
Neelesh

 

[ALuPin]

Hi,

Altera QuartusII tool generates SDF file after fitting (after synthesis) and
I think it is the only way to get the SDF file. I mean how else could
you calculate routing delays etc. before fitting?

 

[Mike Treseler]

Can SDF file be generated after synthesis, if it can, can we see the
delays in the output result using that SDF file. If it can be generated
then which tools support generation after synthesis.

Leonardo can, but the delays are only estimates.

As per my knowledge
SDF files are generated only after P&R.

The P&R .sdf is the only one to use for a gate level sim,
unless you suspect a synthesis error.

Note that you don't need a timing sim at all
for a synchronous design. A functional sim and
a P&R static timing report on fmax is all you need.

-- Mike Treseler

 

[roller]

"neelesh" <[email protected]> wrote in message

Leonardo can, but the delays are only estimates.


The P&R .sdf is the only one to use for a gate level sim,
unless you suspect a synthesis error.

Note that you don't need a timing sim at all
for a synchronous design. A functional sim and
a P&R static timing report on fmax is all you need.

-- Mike Treseler

when you say synchronous, you talk about the reset's too?
and companies agree with not doing a timing sim?

 

[Mike Treseler]

when you say synchronous, you talk about the reset's too?

A reset pulse occurs only at powerup and
should be synchonized to the system clock.
Such a pulse could drive either synch or asynch flop resets.

and companies agree with not doing a timing sim?

That is my opinion.

-- Mike Treseler