Simple combinatorial logic consuming major resources?

Discussion in 'VHDL' started by RZ, Sep 2, 2003.

  1. RZ

    RZ Guest

    Hi,

    I am currently working on a design using Warp & Galaxy.
    When I compile, I see:

    CLOCK/LATCH ENABLE signals 1
    Input REG/LATCH signals 0
    Input PIN signals 2
    Input PINs using I/O cells 0
    Output PIN signals 1

    Total PIN signals 3
    Macrocells Used 12
    Unique Product Terms 16

    Unique Internal Banked Combs 0

    Whan I add this statement:

    PosFet<=ADStr and BDStr;

    I get:

    CLOCK/LATCH ENABLE signals 1
    Input REG/LATCH signals 0
    Input PIN signals 4
    Input PINs using I/O cells 8
    Output PIN signals 2

    Total PIN signals 14
    Macrocells Used 59
    Unique Product Terms 346

    Unique Internal Banked Combs 0

    I must be doing something wrong.
    If I add another combinatorial
    statement I get too many Unique Product Terms.

    Thanks,

    Robert
    rz (at) nikola.Skirtcom.

    Remove your skirt to reply.
     
    RZ, Sep 2, 2003
    #1
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  2. I have some experience with this tool....

    How about posting your code.

    Clyde

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    Clyde R. Shappee, Sep 3, 2003
    #2
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  3. RZ

    RZ Guest

    I just discovered the problem. When I remove the AND gate, the inputs
    to that gate we not being used, they were just internal signals going
    nowhere.
    The compiler was smart enough to know not to waste resources when the
    circuit outputs goes nowhere.

    A newbie stumbles again.

    Thanks,
    -
    Robert
     
    RZ, Sep 3, 2003
    #3
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