Simplifying this combinational logic?

Discussion in 'VHDL' started by Shawn, Feb 25, 2006.

  1. Shawn

    Shawn Guest

    OK, up front.. I'm just getting into VHDL after having used PICs and
    68000's for a bunch of years. It's a bit of a weekend hobby! I have
    a test circuit breadboarded, and I'm trying to get this two case
    decoder working...

    OUT <= "0001" when IN = "00" else
    "0010" when IN = "01" else
    "ZZZZ";

    Is there a way that I could do this instead with just logic
    statements? I'm hung up on how I could assign OUT the different
    values, but I know that I could do something like:

    not IN(0) and not IN(1)

    and...

    IN(1) and not IN(0)

    but how would I assign different values to OUT on each of those lines?

    Any help, pointers, references, or suggestions for good books would be
    appreciated!
     
    Shawn, Feb 25, 2006
    #1
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  2. In general, expressions like
    OUT <= '0' & IN & (not IN(0) and not IN(1));
    would work, though decide for yourself which version is clearer;
    the problem in your example above is finding a logic equation which
    evaluates to "ZZZZ", so at least that arm is best accomplished through a
    "when"... "else" clause.

    Recommended: Peter Ashenden's "The VHDL Cookbook" downloadable from a
    few places, for a quick introduction, and his "Designer's Guide to VHDL"
    for something more comprehensive.

    - Brian
     
    Brian Drummond, Feb 26, 2006
    #2
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  3. Shawn

    Rob Dekker Guest

    Why would you want to 'simplify' this expression ?
    Any synthesis tool will do optimization, so you do not need it for that,
    and for simulation writeing IN="00" is faster than "not IN(0) and not IN(1)".

    The only thing you might want to change is to explicitly let the tool know that
    the two conditions are mutually exclusive. That is done with a selected signal assignment
    (or case statement if you use a 'process') :

    OUT <= with IN select
    "0001" when "00",
    "0010" when "01",
    "ZZZZ" when others ;

    The removes the 'redundant' priority that you put into the conditional assignment,
    and thus could be a bit faster to evaluate for any VHDL tool.

    By the way, if your design contains more than one statement (I have to assume that),
    you might want to consider moving to writing in 'processes'.
    That can be faster for simulation and you can use simple 'if' and 'case' statement to
    achieve the equivalent effect.

    Rob
     
    Rob Dekker, Feb 27, 2006
    #3
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