SRAM vs Cache

[Michael]

Hi all!

What's the difference in "gates density" between a typical
CPU L1 cache and on chip static RAM?

I mean.. how many logic gates are necessary for e.g. 4 KB
of 80486-style L1 cache, and how many for embedded SRAM?

I guess that for the latter it's no less than 65536 gates
(please feel free to provide an exact value!), but for the
L1 cache of equivalent size, how many gates are necessary?
(with gates I mean basic NAND gates).

Thank you!
Mike

 

[Mario Trams]

Michael wrote:

Hello Michael,

What's the difference in "gates density" between a typical
CPU L1 cache and on chip static RAM?

None, actually. CPU cache is usually nothing more than "normal"
static RAM. Some CPUs might use dual-ported RAM in order
to parallelize the interfaces between CPU and cache and
external bus and cache, but I guess that is out of scope of
your question.

I mean.. how many logic gates are necessary for e.g. 4 KB
of 80486-style L1 cache, and how many for embedded SRAM?

Because cache is SRAM, there is no difference. However,
memories are usually not built out of gates, but directly
out of transistors. Of course, they represent boolean
equations, finally.
The common transistor count per SRAM-cell is 6. So for
4KB, you need 4*1024*8*6 = 196608 transistors. Of course,
there are a few more ones needed for decoding logic etc.

If you want to think in NAND-Gates, such one is built out of
4 transistors normally (assuming a push-pull stage). So your
4KB RAM needs an equivalent of around 50000 gates. But again,
SRAMs are not built from gates as such!

I guess that for the latter it's no less than 65536 gates
(please feel free to provide an exact value!), but for the
L1 cache of equivalent size, how many gates are necessary?
(with gates I mean basic NAND gates).

Dito.

Regards,
Mario

 

[Uncle Noah]

Michael wrote:

Hello Michael,


None, actually. CPU cache is usually nothing more than "normal"
static RAM.

VERY WRONG. Caches incorporate special "tag comparison" logic. They
are larger than their SRAM counterparts and more power expensive. For
power it is:
ROM < SRAM (scratchpad) < cache.

Because cache is SRAM, there is no difference.

What can i say about that? Then we should you caches as often as
possible. No wonder why 512KB of L2 cache is so expensive...

Uncle "The G.B. Man" Noah

 

[Mario Trams]

VERY WRONG. Caches incorporate special "tag comparison" logic. They
are larger than their SRAM counterparts and more power expensive. For
power it is:
ROM < SRAM (scratchpad) < cache.

Of course, that is an important management aspect of a cache
as a whole (and I do know very well how caches are working .
To justify myself, in my post I referred just to the actual data
cache because it appeared to be a sufficient answer to the
original question.

What can i say about that? Then we should you caches as often as
possible. No wonder why 512KB of L2 cache is so expensive...

Dito. Again, this refers just to the actual data storage excluding
management aspects.

Regards,
Mario

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Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
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[Mario Trams]

Of course, that is an important management aspect of a cache
as a whole (and I do know very well how caches are working .
To justify myself, in my post I referred just to the actual
data cache

^^^^^^^^^^ should read "data storage memory of the cache"

Mario