Synchronizing two different clocks

[john]

Hello,

My application needs to have two different clock synchronized together.
The FPGA is getting the data into the 48 BIT buffer with every rising
edge of USB clock and serially outputing it on a different clock of
different frequency generated by a clock generator. How can I
synchronize the writing and reading of the buffer and synchronize it
with out using any FIFO. The application will be real time. like
getting the into and then out of the RAM.

Please advice!

John

 

[Mike Treseler]

The FPGA is getting the data into the 48 BIT buffer with every rising
edge of USB clock and serially outputing it on a different clock of
different frequency generated by a clock generator. How can I
synchronize the writing and reading of the buffer and synchronize it
with out using any FIFO.

I would create a synchronous strobe of one fast clock cycle
duration near the middle of the buffer valid time.

-- Mike Treseler

 

[john]

Hi Mike,

I did not follow you completely, Would you explain a little more.

John

 

[Mike Treseler]

I did not follow you completely, Would you explain a little more.

Have a look at this section
....
when RECEIVE =>
inc_tic_count;
sample_time:if bit_done then -- at center of bit
sample_tp_sim_only_v := true; -- to check sample centering
RxBitSampleCount_v := 0; -- This overwrites the carry value
grab_a_bit: Rx_v(RxBitCount_v) := serialInRetimed_v.F3;
inc_rx_count:RxBitCount_v := RxBitCount_v+1;
end_of_payload:if RxBitCount_v = char_len_g then
RxState_v := STOP;
end if end_of_payload;
else
sample_tp_sim_only_v := false; -- sim only
end if sample_time;
....

of the reference design here
http://home.comcast.net/~mike_treseler/

Run the testbench like this:
vsim -Gtb_tics_g=42 -c test_uart -do "run -all; exit"
to see the centering.

-- Mike Treseler

 

[Mike Treseler]

Run the testbench like this:
vsim -Gtb_tics_g=42 -c test_uart -do "run -all; exit"
to see the centering.

Oops. Can't see anything that way.
Better make that:

vsim -Gtb_tics_g=42 test_uart
then "do uart.do" from modelsim prompt

-- Mike Treseler

 

[john]

Hi Mike,

I read the example but could not undersatnd it completely. The USB_CLK
is getting the data in at each falling edge of the clock. The USB data
bus is eight bit wide. So, It will take 6 clock cycles to fill the 48
bit parallel data. Now, I have to use the other clock to serial out the
first set of eight bits serially out before USB clk replaces the first
set of eight bits. What algorithm you propose for this problem with out
using FIFO?

Thanks
John

 

[Mike Treseler]

I read the example but could not undersatnd it completely. The USB_CLK
is getting the data in at each falling edge of the clock. The USB data
bus is eight bit wide. So, It will take 6 clock cycles to fill the 48
bit parallel data. Now, I have to use the other clock to serial out the
first set of eight bits serially out before USB clk replaces the first
set of eight bits.

The slow process will collect 6 bytes and
transfer the 48 bits into a slow register once per cycle.
It will also generate a wide strobe during the third byte.

The fast process will synchronize the wide strobe
and detect the rising edge.

_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
___________
________/ \__________
__________-------------__________
___________--___________________

This fast strobe will be used to clock enable
load a 48 bit fast shift register.

Of course, this will only work if the fast
clock is fast enough.

What algorithm you propose for this problem with out
using FIFO?

Trial and error simulation.
Start with the detector and
add a bit at a time.
Good luck.

-- Mike Treseler

 

[Pascal Peyremorte]

john a écrit :

Hello,

My application needs to have two different clock synchronized together.
The FPGA is getting the data into the 48 BIT buffer with every rising
edge of USB clock and serially outputing it on a different clock of
different frequency generated by a clock generator. How can I
synchronize the writing and reading of the buffer and synchronize it
with out using any FIFO. The application will be real time. like
getting the into and then out of the RAM.

Please advice!

John

Hello John,

Do a simple handshake.

Create an "ouput_clock_enable" that is set only by "data_loaded" (based from the
parallel input clock) and reset only by "shift register empty" (based from the
serial output clock).

While this "ouput_clock_enable" is high, you cannot write data to the shift
register.

A such interlocked handshake will assure you that you will never have a
collision between the two clocks, and that transmission will start in less than
1 output clock cycle.

While this "ouput_clock_enable" is high, if the pending data is already latched,
you have nothing to do (1 level fifo). Else you have to latch it until the
serializer will be free.

In the case of the multibyte packet to send is too large to be sent byte per
byte because the serial clock is not enough fast, you can do
- an input fifo that can handle your full packet
- a wider register that can load your full packet.

In both cases, you need the same hardware resources...

Pascal

 

[john]

Hi Mike,
I came up with the following code
Process ( state, Reset)
Begin
Case state is
when G0=>
par_buff_USB (7 downto 0)<= USB_Data (7 downto 0);
long_strb <= '0';
nextstate <=G1;

when G1=>
par_buff_USB (15 downto 8)<= USB_Data (7 downto 0);
long_strb <= '0';
nextstate <=G2;

when G2=>
par_buff_USB (23 downto 16)<= USB_Data (7 downto 0);
long_strb <= '0';
nextstate<=G3;

when G3=>
par_buff_USB (31 downto 24)<= USB_Data (7 downto 0);
long_strb <= '1';
nextstate<=G4;

when G4=>
par_buff_USB (39 downto 32)<= USB_Data (7 downto 0);
long_strb <= '1';
nextstate<=G5;

when G5=>
par_buff_USB (47 downto 40)<= USB_Data (7 downto 0);
long_strb <= '1';
nextstate<=G0;

when others =>
nextstate<=G0;
End case;
End Process;
-------------------------------------------------
Process (Reset, USB_CLK)
Begin
If ( Reset = '1') Then
state <= G0;
Elsif (USB_CLK 'Event And USB_CLK = '0') Then
state <= nextstate;
End If;
End Process;
--------------------------------------------------
Process (Fast_CLK, long_strb)
Begin
If (Fast_CLK 'Event And Fast_CLK = '1') Then
If (long_strb = '1') Then
Fast_strb <= '1';
else
Fast_strb <= '0';
End If;
End If;
End Process;

Process ( Fast_CLK, Fast_strb )
Begin
If (Fast_CLK 'Event And Fast_CLK = '1') Then
If ( Fast_strb = '1') Then
Fast_ser_buff<= par_buff_USB;
End If;
End If;
End Process;

I am generating the strobe signal when the third byte get into the
buffer and I am also able to generate the Fast strobe signal in
response to the slow strobe signal but I could not understand that what
do you mean by
"The fast process will synchronize the wide strobe and detect the
rising edge.
This fast strobe will be used to clock enable load a 48 bit fast shift
register."
Please advice!
John

 

[Mike Treseler]

"The fast process will synchronize the wide strobe and detect the
rising edge.

wide >-----[dq]-[dq]----wideq----[0 to 1 detect]--------load
fast_clk---[> ]-[> ]-------------[> * ]

*See procedure "rising" in rising level counter here:
http://home.comcast.net/~mike_treseler/

This fast strobe will be used to clock enable load a 48 bit fast shift
register."

pipe the 48 bit words and load s/r with previous value.
You will need a simulator to get the shift/load right.

-- Mike Treseler

 

[john]

Hi,

What is DQ or wideQ?

John

"The fast process will synchronize the wide strobe and detect the
rising edge.

wide >-----[dq]-[dq]----wideq----[0 to 1 detect]--------load
fast_clk---[> ]-[> ]-------------[> * ]

*See procedure "rising" in rising level counter here:
http://home.comcast.net/~mike_treseler/

This fast strobe will be used to clock enable load a 48 bit fast shift
register."

pipe the 48 bit words and load s/r with previous value.
You will need a simulator to get the shift/load right.

-- Mike Treseler

 

[john]

Hi Pascal,
The correct problem is given below
I read the example but could not undersatnd it completely. The USB_CLK
is getting the data in at each falling edge of the clock. The USB data

bus is eight bit wide. So, It will take 6 clock cycles to fill the 48

bit parallel data. Now, I have to use the other clock to serial out
the
first set of eight bits serially out before USB clk replaces the first

set of eight bits.

What do you think about mike's solution?

John