Synchronous processes and delays

Discussion in 'VHDL' started by Thomas, Jul 6, 2003.

  1. Thomas

    Thomas Guest

    let's assume 2 entities:

    a, with input_a and output_a as signals
    b, with input_b and output_b as signals

    now, let's assume in my design, both processes are synchronous but output_a
    is connected to input_b;
    if the propagation time is high between input_a and output_a, what happens?

    - process b is run only when input_b's ready?


    - when the clock ticks, process b takes whatever's in input_b, meaning it
    will run one tick after process a?

    in practice, the case I have is a bus decoding that is doing a bunch of
    operations and then creating chipselect signals to the various parts of the
    design, but these have to run on the same clock tick as well
    Thomas, Jul 6, 2003
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  2. Thomas

    Thomas Guest

    so, this means if I decode the address during rising phi2, I can't really
    do anything synchronous, requiring the use of the decoded information, at
    the same time, I have to keep all the operations for the falling edge
    (right before hold time), is that right?
    Thomas, Jul 6, 2003
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  3. Thomas

    Mario Trams Guest

    Better say: "register the decoding result at rising Phi2"
    Basically Yes. The first opportunity to evaluate the signals
    registered at the rising Phi2 is at the falling Phi2.
    (Btw.: That's the nature of the 6502 architecture. It is pipelined
    like a master-slave flip flop.)

    Note that a registered (synchronous) address decoding on the 6502
    bus is not necessarily required.

    If you need to do some clocked operations in between rising and falling
    clock edges, you should consider using a higher clock for your logic
    (say 2 times CPU-clock).


    Digital Force / Mario Trams

    Chemnitz University of Technology
    Dept. of Computer Science Tel.: (+49) 371 531 1660
    Chair of Computer Architecture Fax.: (+49) 371 531 1818
    Mario Trams, Jul 6, 2003
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