Folks,\n\nFor my cryptography course I had to construct an AES core in VHDL. I\nduely constructed one and have verified that it works and synthesises\nfine.\n\nLater it transpired that one of my classmates had built one with\nsignificantly better throughput; never one to turn down a challenge I\npared down my implementation and made a composite entity with three\ncores, a phase-shifted clock divider and a multiplexer on the output.\n\nWhen I synthesize this (Synplify Pro 7.5.1) and look at the performance\nsummary I get:\n\nPerformance Summary\n*******************\n\n\nWorst slack in design: 955.357\n\nRequested Estimated Requested\nEstimated Clock Clock\nStarting Clock Frequency Frequency Period\nPeriod Slack Type Group\n-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\n-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\nAES|clk 1.0 MHz 22.4 MHz 1000.000\n44.643 955.357 inferred Inferred_clkgroup_3\nAES|clks_inferred_clock 1.0 MHz 71.6 MHz 1000.000\n13.965 986.035 inferred Inferred_clkgroup_0\nAES|clks_inferred_clock 1.0 MHz 74.2 MHz 1000.000\n13.481 986.519 inferred Inferred_clkgroup_2\nAES|clks_inferred_clock 1.0 MHz 71.7 MHz 1000.000\n13.945 986.055 inferred Inferred_clkgroup_1\n========================================================================\n===========================================================\n\nI'm slightly confused as to the meaning of this, on its own my AES core\nwill clock at about 60Mhz. The clock divider puts out three phase\nshifted clocks with a 1:2 duty cycle so I can sort of understand the\ninferred clocks being able to go a bit faster (longer time to setup\netc).\n\nHowever, does this really mean that my main clock will only work at\n22.4Mhz?? Why so slow? This means that the individual clocks will run at\n6Mhz. It's only a simple 3 register clock divider that on its own\nsynthesises to an expected performance of 150Mhz. All the main clock\ndoes is drive the clock divider and the output multiplexer.\n\nAm I reading this wrong? Is it something to do with clock buffering?\nAnybody got any suggestions for how to get my multicore system to run at\na more sensible clock rate? (I'll add at this point that it is 66 layer\npipelined, I have thinned out all the logic I can find, the limiting\nfactor on the clock speed for the main core is a big feedback loop which\nis unavoidable).\n\nThanks in advance guys,\n\nAndrew.