is there any method to automatically put (during loading) in a register of a
synthetised FPGA a time reference,
to be able to verify later the running version (by JTAG, for example) ?
I don't know any way to hack this sort of thing into the bit stream,
unless you can do it by setting some ROM initialisation value. Try
asking on comp.arch.fpga where the FPGA implementation gurus live.
However, I *do* know how to do it at the synthesis stage, without
interfering with your VHDL source code.
If your synthesis tool has a Tcl scripting shell (true for Synplify,
Leonardo, Precision, Synopsys DC and probably many others) then you
can do it from the synthesis script. Set up an integer generic in
your top-level design, and use that generic to construct your date tag
within the logic. Configure that generic from your script at elaboration.
Tcl can easily construct an integer based on the date and time. This
little Tcl proc constructs an integer whose value is the number of hours
since midnight on the 1st Jan 2000, displays it in both decimal and hex,
and returns the value so that you can use it elsewhere in the script:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
proc hours_since_millennium {} {
set now [clock seconds]
set millennium [clock scan 01-jan-2000]
set diff [expr {($now - $millennium) / 3600}]
puts "Hours since millennium: $diff = [format 0x%04X $diff]"
return $diff
}
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Suppose your top-level VHDL is just this...
~~~~~~~~~~~ file: date.vhd ~~~~~~~~~~~~~~~~~~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity has_ID is
generic (ID_value: natural := 0);
port (ID: out std_logic_vector(15 downto 0));
end;
architecture rtl of has_ID is
begin
ID <= std_logic_vector(to_unsigned(ID_value, ID'length));
end;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
A suitable synthesis script for Leo Spectrum looks something
like this... other tools will be broadly similar.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# Read without elaboration, so we can set the generic later
read -technology "xis2" -dont_elaborate
C:/jseb/oddments/vhdl/Fun/date.vhd }
# Now elaborate the top-level, with appropriate setting for the generic
elaborate has_ID -architecture rtl -generics
ID_value=[hours_since_millennium]
# Finally, do your pre-optimize and optimize steps as usual.
....
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
HTH
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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