Synthesis of VHDL RTL including recursive functions

Discussion in 'VHDL' started by gpi5, Nov 9, 2004.

  1. gpi5

    gpi5 Guest

    Hi

    When a VHDL module with recursive functions is synthetised, what is
    exactly happening?
    The result is available during the same clock cycle, so I would expect the
    synthesis tool to translate the recursive nature of the algorithm into a
    'spacial' algorithm (e.g. if the recusion has a depth of 10, then there
    will be 10 'stages' on the silicon). Am I totally wrong here?

    Where can I find further details on that?
    Thanks,
    gil
     
    gpi5, Nov 9, 2004
    #1
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  2. Loops of all types are an editing convenience.
    All loops are unrolled long before anything physical happens.
    http://groups.google.com/groups?q=vhdl+recursion+OR+recursive


    -- Mike Treseler
     
    Mike Treseler, Nov 9, 2004
    #2
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