Synthesizing a design with RAM.

Discussion in 'VHDL' started by Kelvin @ Singapore, Sep 9, 2003.

  1. Hi, all:

    What is the right procedure to synthesize a design with a RAM when I don't
    have a .db model for the
    RAM? I only have the datasheet and .lib file generated from a RAM-Generator
    supplied by the fab.

    I could use Library Compiler to convert .lib into .db but with a warning
    saying "LC is not enabled and
    cell functionalities are ignored". Does this .db file include the timing
    checks on the IO of the RAM or
    just a black box with no functionality and no timing?



    Best Regards,
    Kelvin
     
    Kelvin @ Singapore, Sep 9, 2003
    #1
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