System Verilog

Discussion in 'VHDL' started by nivparsons, Mar 14, 2013.

  1. nivparsons

    nivparsons Guest

    I'm just starting to use SV Assertions with my VHDL code in Questa.
    Is there a group that supports this kind of thing? TheSystem Verilog group I found seems unused?

    Regards, Niv.
    nivparsons, Mar 14, 2013
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  2. nivparsons

    HT-Lab Guest

    I would try the Verification Guild:

    HT-Lab, Mar 15, 2013
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