SystemC std_logic resolved type

Discussion in 'VHDL' started by zoro, Jul 3, 2003.

  1. zoro

    zoro Guest

    Hi,
    I have encountred a problem while working with resolved sc_logic type.
    Considering using resolved sc_logic even for signals, when I assign a
    new value to such signals their value change to 'X'.

    for example in the following code, "sa" signal gets 'X' at 25 ns
    instead of '1'; This case doesn't happen for a,b,c signals.

    -------Header
    SC_MODULE (testbench) {

    sc_signal_rv<8> a;
    sc_signal_rv<8> b;
    sc_signal_rv<8> c;
    sc_signal_resolved sa;
    sc_signal_resolved sb;
    sc_signal_resolved sc;

    sc_signal_rv<8> z;

    void p1 ();
    ....
    SC_CTOR(testbench) {

    sa = (sc_logic )'0';
    SC_THREAD(p1);

    SC_THREAD(p2);
    ....
    };
    #endif
    ---------CPP
    void testbench::p1(){
    while(true){
    sa = (sc_logic )'0';
    wait(25,SC_NS);
    sa = (sc_logic )'1';
    wait(25,SC_NS);
    }
    }
     
    zoro, Jul 3, 2003
    #1
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  2. zoro

    Alan Fitch Guest

    I don't think we can answer that question without
    knowing what happens in process p2().

    I suggest you post the complete code to the "SystemC Help"
    web forum at www.systemc.org,

    kind regards

    Alan


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    Alan Fitch, Jul 3, 2003
    #2
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  3. The problem might be that you should typecast 1 in stead of '1'.

    /Nicolai
     
    =?ISO-8859-1?Q?Nicolai_J=F8rgensen?=, Jul 5, 2003
    #3
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