Testing an AHB slave after synthesis

[Ludek]

Hi people,

I develop an AHB slave with a framework. So the slave has generally one input (ahb_slv_in_type) and one output (ahb_slv_out_type). But (as most of you know) this is a wide bus, therefore after synthesis I get lots of single signals and I cannot simulate it with the framework again. Is there any way to keep these signals in one bus as it was before synthesis? I use Synplify PRO and ModelSim but I have not found in manuals anything helpful.

Any help is very appreciated.
Thanks