I need to find the difference between two signal's arrival time with the
resolution of 200 ps.
I'm using Virtex-6 XC6VLX240T-ff1156-1.
I think I'll be required to build a TDC.
Can anyone help me about how to start that?
--BLue39
There are many ways to build a time-to-digital converer (TDC). Many of
them require lots of analog circuitry, but this is a VHDL newsgroup and
you want to use an FPGA, so here's a completely digital approach:
Virtex-6 *LXT-1 has GTX transceivers that will work at 5Gb/s.
You can put them in "lock to reference" mode that disables the CDR and
can be used to sample the input signals at 5Gb/s.
You'll need to disable every feature in the transceiver that causes
latency to be variable or unknown (the Elastic Buffer in particular).
Either that, or use some sort of external calibration to null out the
latency difference between the two transceivers.
The output of the transceivers (inside the FPGA fabric) will be a
parallel bus at a much lower clock frequency, e.g. a 20 bit wide datapath
clocked at 250MHz or a 16 bit datapath clocked at 312.5MHz.
It should be fairly easy for you to create logic that decodes the bus
contents to locate the transistions caused by each signal's arrival time,
then computes the difference.
If you have problems getting logic to work at 312.5MHz, try adding a
small circuit to change the bus to twice the width at half the clock
frequency, e.g. 32 bit at 156.25MHz.
Regards,
Allan
