This spike problem can only arise due to different delays in the "real" circuit.
You can get rid of this by moving the outval behind the rising_edge(Clk). In other words will it cost you an extra F/F in the design.
Your dealing with a moore output anyway so this shouldn't give you any delays.
Best regards
Jeppe
Your velcome
(Glad to see its possible to include code and figures)
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