Type conversion and std_logic_vector incrment

[Govinda]

Hi,

I am a VHDL newbie and need help on some things that might be trivial for the experts in this group.
How do we increment or decrement a std_logic_vector? if I try to do something like
temp <= temp + 1;

it gives an error saying couldn't find infix operator '+'. I get similar errors for checking conditions like
if (temp1 <= temp2) where temp1 and temp2 are both std_logic_vectors.

Are these operations limited to integer/natural number types only? If so, how do we synthesize these conditional statements?

Thanks for your time

G